297 lines
9.1 KiB
Scala
297 lines
9.1 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import scala.math._
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import Util._
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class DpathBTBIO extends Bundle
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{
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val current_pc = UFix(INPUT, VADDR_BITS);
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val hit = Bool(OUTPUT);
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val target = UFix(OUTPUT, VADDR_BITS);
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val wen = Bool(INPUT);
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val clr = Bool(INPUT);
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val invalidate = Bool(INPUT);
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val correct_pc = UFix(INPUT, VADDR_BITS);
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val correct_target = UFix(INPUT, VADDR_BITS);
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}
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// fully-associative branch target buffer
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class rocketDpathBTB(entries: Int) extends Component
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{
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val io = new DpathBTBIO
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val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU
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var hit_reduction = Bool(false)
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val hit = Bool()
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val update = Bool()
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var update_reduction = Bool(false)
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val hits = Vec(entries) { Bool() }
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val updates = Vec(entries) { Bool() }
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val targets = Vec(entries) { Reg() { UFix() } }
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val anyUpdate = updates.toBits.orR
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for (i <- 0 until entries) {
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val tag = Reg() { UFix() }
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val valid = Reg(resetVal = Bool(false))
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hits(i) := valid && tag === io.current_pc
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updates(i) := valid && tag === io.correct_pc
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when (io.wen && (updates(i) || !anyUpdate && UFix(i) === repl_way)) {
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valid := Bool(false)
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when (!io.clr) {
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valid := Bool(true)
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tag := io.correct_pc
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targets(i) := io.correct_target
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}
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}
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}
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io.hit := hits.toBits.orR
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io.target := Mux1H(hits, targets)
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}
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class Status extends Bundle {
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val im = Bits(width = 8)
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val zero = Bits(width = 7)
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val vm = Bool()
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val s64 = Bool()
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val u64 = Bool()
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val s = Bool()
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val ps = Bool()
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val ec = Bool()
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val ev = Bool()
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val ef = Bool()
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val et = Bool()
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}
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object PCR
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{
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// commands
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val SZ = 3
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val X = Bits("b???", 3)
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val N = Bits(0,3)
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val F = Bits(1,3) // mfpcr
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val T = Bits(4,3) // mtpcr
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val C = Bits(6,3) // clearpcr
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val S = Bits(7,3) // setpcr
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// regs
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val STATUS = 0
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val EPC = 1
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val BADVADDR = 2
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val EVEC = 3
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val COUNT = 4
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val COMPARE = 5
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val CAUSE = 6
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val PTBR = 7
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val SEND_IPI = 8
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val CLR_IPI = 9
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val COREID = 10
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val IMPL = 11
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val K0 = 12
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val K1 = 13
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val VECBANK = 18
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val VECCFG = 19
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val RESET = 29
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val TOHOST = 30
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val FROMHOST = 31
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}
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class PCR(implicit conf: RocketConfiguration) extends Component
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{
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val io = new Bundle {
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val host = new HTIFIO(conf.lnConf.nClients)
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val r = new ioReadPort(conf.nxpr, conf.xprlen)
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val w = new ioWritePort(conf.nxpr, conf.xprlen)
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val status = new Status().asOutput
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val ptbr = UFix(OUTPUT, PADDR_BITS)
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val evec = UFix(OUTPUT, VADDR_BITS)
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val exception = Bool(INPUT)
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val cause = UFix(INPUT, 6)
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val badvaddr_wen = Bool(INPUT)
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val vec_irq_aux = Bits(INPUT, conf.xprlen)
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val vec_irq_aux_wen = Bool(INPUT)
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val pc = UFix(INPUT, VADDR_BITS+1)
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val eret = Bool(INPUT)
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val ei = Bool(INPUT)
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val di = Bool(INPUT)
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val ptbr_wen = Bool(OUTPUT)
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val irq_timer = Bool(OUTPUT)
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val irq_ipi = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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val vecbank = Bits(OUTPUT, 8)
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val vecbankcnt = UFix(OUTPUT, 4)
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val vec_appvl = UFix(INPUT, 12)
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val vec_nxregs = UFix(INPUT, 6)
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val vec_nfregs = UFix(INPUT, 6)
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}
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import PCR._
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val reg_epc = Reg{Bits(width = conf.xprlen)}
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val reg_badvaddr = Reg{Bits(width = conf.xprlen)}
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val reg_ebase = Reg{Bits(width = conf.xprlen)}
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val reg_count = WideCounter(32)
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val reg_compare = Reg{Bits(width = 32)}
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val reg_cause = Reg{Bits(width = io.cause.getWidth)}
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val reg_tohost = Reg(resetVal = Bits(0, conf.xprlen))
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val reg_fromhost = Reg(resetVal = Bits(0, conf.xprlen))
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val reg_coreid = Reg{Bits(width = 16)}
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val reg_k0 = Reg{Bits(width = conf.xprlen)}
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val reg_k1 = Reg{Bits(width = conf.xprlen)}
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val reg_ptbr = Reg{UFix(width = PADDR_BITS)}
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val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits)
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val reg_error_mode = Reg(resetVal = Bool(false))
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val reg_status = Reg{new Status} // reset down below
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val r_irq_timer = Reg(resetVal = Bool(false))
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val r_irq_ipi = Reg(resetVal = Bool(true))
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val rdata = Bits();
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val host_pcr_req_valid = Reg{Bool()} // don't reset
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val host_pcr_req_fire = host_pcr_req_valid && !io.r.en && !io.w.en
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val host_pcr_rep_valid = Reg{Bool()} // don't reset
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val host_pcr_bits = Reg{io.host.pcr_req.bits.clone}
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io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
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io.host.pcr_rep.valid := host_pcr_rep_valid
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io.host.pcr_rep.bits := host_pcr_bits.data
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when (io.host.pcr_req.fire()) {
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host_pcr_req_valid := true
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host_pcr_bits := io.host.pcr_req.bits
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}
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when (host_pcr_req_fire) {
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host_pcr_req_valid := false
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host_pcr_rep_valid := true
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host_pcr_bits.data := rdata
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}
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when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
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val raddr = Mux(io.r.en, io.r.addr, host_pcr_bits.addr)
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val wen = io.w.en || !io.r.en && host_pcr_req_valid && host_pcr_bits.rw
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val waddr = Mux(io.w.en, io.w.addr, host_pcr_bits.addr)
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val wdata = Mux(io.w.en, io.w.data, host_pcr_bits.data)
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io.status := reg_status
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io.ptbr_wen := wen && waddr === PTBR
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io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix
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io.ptbr := reg_ptbr
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io.host.debug.error_mode := reg_error_mode
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io.r.data := rdata
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io.vecbank := reg_vecbank
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var cnt = UFix(0,4)
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for (i <- 0 until 8)
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cnt = cnt + reg_vecbank(i)
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io.vecbankcnt := cnt(3,0)
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when (io.badvaddr_wen || io.vec_irq_aux_wen) {
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val wdata = Mux(io.badvaddr_wen, io.w.data, io.vec_irq_aux)
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val (upper, lower) = Split(wdata, VADDR_BITS)
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val sign = Mux(lower.toFix < Fix(0), upper.andR, upper.orR)
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reg_badvaddr := Cat(sign, lower).toFix
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}
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when (io.exception) {
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when (!reg_status.et) {
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reg_error_mode := true
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}
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reg_status.s := true
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reg_status.ps := reg_status.s
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reg_status.et := false
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reg_epc := io.pc.toFix
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reg_cause := io.cause
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}
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when (io.eret) {
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reg_status.s := reg_status.ps
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reg_status.et := true
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}
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when (reg_count === reg_compare) {
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r_irq_timer := Bool(true);
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}
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io.irq_timer := r_irq_timer;
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io.irq_ipi := r_irq_ipi;
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io.host.ipi_req.valid := io.w.en && io.w.addr === SEND_IPI
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io.host.ipi_req.bits := io.w.data
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io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
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when (host_pcr_req_fire && !host_pcr_bits.rw && host_pcr_bits.addr === TOHOST) { reg_tohost := UFix(0) }
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0)
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val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
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rdata := AVec[Bits](
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reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase,
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reg_count, reg_compare, read_cause, read_ptbr,
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reg_coreid/*x*/, read_impl/*x*/, reg_coreid, read_impl,
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reg_k0, reg_k1, reg_k0/*x*/, reg_k1/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
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)(raddr)
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when (wen) {
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when (waddr === STATUS) {
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reg_status := new Status().fromBits(wdata)
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reg_status.zero := 0
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if (!conf.vec) reg_status.ev := false
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if (!conf.fpu) reg_status.ef := false
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if (!conf.rvc) reg_status.ec := false
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}
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when (waddr === EPC) { reg_epc := wdata(VADDR_BITS,0).toFix }
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when (waddr === EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toFix }
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when (waddr === COUNT) { reg_count := wdata.toUFix }
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when (waddr === COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
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when (waddr === COREID) { reg_coreid := wdata(15,0) }
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when (waddr === FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
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when (waddr === TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
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when (waddr === CLR_IPI) { r_irq_ipi := wdata(0) }
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when (waddr === K0) { reg_k0 := wdata; }
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when (waddr === K1) { reg_k1 := wdata; }
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when (waddr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (waddr === VECBANK) { reg_vecbank:= wdata(7,0) }
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}
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io.host.ipi_rep.ready := Bool(true)
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when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
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when (reset) {
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reg_status.et := false
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reg_status.ef := false
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reg_status.ev := false
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reg_status.ec := false
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reg_status.ps := false
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reg_status.s := true
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reg_status.u64 := true
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reg_status.s64 := true
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reg_status.vm := false
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reg_status.zero := 0
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reg_status.im := 0
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}
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}
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class ioReadPort(d: Int, w: Int) extends Bundle
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{
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val addr = UFix(INPUT, log2Up(d))
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val en = Bool(INPUT)
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val data = Bits(OUTPUT, w)
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override def clone = new ioReadPort(d, w).asInstanceOf[this.type]
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}
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class ioWritePort(d: Int, w: Int) extends Bundle
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{
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val addr = UFix(INPUT, log2Up(d))
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val en = Bool(INPUT)
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val data = Bits(INPUT, w)
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override def clone = new ioWritePort(d, w).asInstanceOf[this.type]
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}
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