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Commit Graph

5427 Commits

Author SHA1 Message Date
Henry Cook
f35a6a574f Add a queue on released data coming in to L2 2015-03-16 13:25:01 -07:00
Henry Cook
b72230a9f0 PutBlock bugfix 2015-03-16 00:09:55 -07:00
Henry Cook
f6d1a2fb76 No more self-probes required 2015-03-16 00:09:38 -07:00
Henry Cook
23a6b007c1 Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring 2015-03-15 23:10:51 -07:00
Henry Cook
c03976896e separate queues for resp tag and data 2015-03-15 17:58:17 -07:00
Andrew Waterman
e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Andrew Waterman
6e540825b2 Use entire 12-bit CSR address 2015-03-14 02:15:24 -07:00
Yunsup Lee
ebbd14254c uncached port should be a HeaderlessUncachedTileLinkIO type 2015-03-13 02:12:23 -07:00
Yunsup Lee
3a78ca210d bugfix in uncached TL to TL convertors 2015-03-12 16:33:41 -07:00
Henry Cook
51e4cd7616 Added UncachedTileLinkIO port to RocketTile, simplify arbitration 2015-03-12 16:30:04 -07:00
Henry Cook
8181262419 clean up incoherent and probe flags 2015-03-12 16:22:14 -07:00
Henry Cook
dcc84c4dd3 arbiter probe ready bugfix 2015-03-12 16:02:51 -07:00
Yunsup Lee
2c31ed6426 previous bug fix for meta data writeback wasn't quite right 2015-03-12 15:34:20 -07:00
Yunsup Lee
5e40c8ba77 write back meta data when cache miss even when coherence meta data is clean 2015-03-12 14:36:46 -07:00
Albert Ou
8f8022379c Fix AMO opcode extraction 2015-03-11 23:24:58 -07:00
Albert Ou
f75126c39c Require self probes for all built-in Acquire types
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
2015-03-11 23:24:58 -07:00
Yunsup Lee
ea018b3d84 stall rocket decode when not rocc ready 2015-03-11 22:33:03 -07:00
Henry Cook
1aff919c24 added prefetchAck Grant type 2015-03-11 17:32:06 -07:00
Henry Cook
059575c334 cleanup mergeData and prep for cleaner data_buffer in L2 2015-03-11 15:43:41 -07:00
Henry Cook
b4ed1d9121 Add builtin prefetch types to TileLink 2015-03-11 14:28:17 -07:00
Yunsup Lee
3ab1aca7de L2 subblock access bugfix 2015-03-11 01:56:47 -07:00
Colin Schmidt
e293d89035 fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/ 2015-03-10 10:28:05 -07:00
Henry Cook
17072a0041 L2 Writeback bugfix 2015-03-10 01:15:03 -07:00
Henry Cook
a1f04386f7 Headerless TileLinkIO and arbiters 2015-03-09 16:34:59 -07:00
Henry Cook
95aa295c39 Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS 2015-03-09 16:34:43 -07:00
Henry Cook
002f1a1b39 pin outer finish header 2015-03-09 12:40:37 -07:00
Henry Cook
df79e7ff8d secondary miss bug 2015-03-05 15:51:18 -08:00
Henry Cook
8e41fcf6fc reduce MemIFTag size, enable non pow2 HellaFLowQueue size 2015-03-05 15:51:02 -08:00
Henry Cook
b36d751250 sret bugfix: bypass arbiter 2015-03-05 13:14:16 -08:00
Henry Cook
35532420a8 Merge pull request #6 from ccelio/master
Clarified ptw/tlb/sret/cache I/O bundles
2015-03-03 18:01:26 -08:00
Christopher Celio
06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Christopher Celio
5d07733057 Removed TLBPTWIO from the io.cpu bundle for icache/dcache 2015-03-03 16:40:39 -08:00
Henry Cook
1bed6ea498 New metadata-based coherence API 2015-02-28 17:32:03 -08:00
Henry Cook
1e0c16c557 new metadata api 2015-02-28 17:00:32 -08:00
Yunsup Lee
4f57985198 change organization to riscv 2015-02-17 14:43:11 -08:00
Henry Cook
0a8722e881 bugfix for indexing DataArray of of small L2 2015-02-17 00:37:40 -08:00
Henry Cook
0b131173e6 WritebackUnit multibeat control logic bugfix 2015-02-16 10:59:57 -08:00
Henry Cook
0c66e70f14 cleanup of conflicts; allocation bugfix 2015-02-06 13:20:44 -08:00
Albert Magyar
09cd555f29 Update riscv-tools pointer to prepare for HPCA workshop. 2015-02-04 13:29:04 -08:00
Henry Cook
7b86ea17cf rename L2HellaCache to L2HellaCacheBank 2015-02-03 19:38:01 -08:00
Henry Cook
aa46b8b72d Slightly refactor TLBResp 2015-02-03 19:32:37 -08:00
Stephen Twigg
3b3250339a Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:15:01 -08:00
Stephen Twigg
3d35ccd401 Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
Henry Cook
57340be72b doc update 2015-02-02 01:11:13 -08:00
Henry Cook
6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f Offset AMOs within beat and return old value 2015-02-02 00:22:21 -08:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel 2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128 state machine bug on uncached write hits 2015-02-01 20:29:23 -08:00