e652821962
Use correct kind of TileLink arbiter
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It was "correct" before, but broke Chisel3 build.
2016-03-28 22:53:47 -07:00
015992bc9e
no longer need MIFMasterTagBits
2016-03-28 12:24:11 -07:00
8e7f18084b
switch RTC to use TileLink instead of AXI
2016-03-28 12:23:16 -07:00
34852e406d
fix bug in NastiRouter
2016-03-28 12:22:43 -07:00
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
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separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
f526d380fd
separate btb response mask from the frontend mask
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It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
ed280fb3de
Remove empty when statement (???)
2016-03-25 15:52:18 -07:00
1ae6d09751
Slightly ameliorate D$->I$ critical path via scoreboard
2016-03-25 15:29:32 -07:00
6c48dc3471
Use more sensible knob values for SmallConfig
2016-03-25 14:18:24 -07:00
cce89f5fbc
Bump rocket
2016-03-25 14:18:15 -07:00
a4685a073f
Don't instantiate PTW when UseVM=false
2016-03-25 14:17:25 -07:00
27b3cca046
Discover D$, PTW port counts dynamically
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This is a generator, after all...
2016-03-25 14:16:56 -07:00
af3bc1cb79
don't use ROM for partial writemask regression
2016-03-25 14:06:06 -07:00
5372f181b1
add in missing connections for regression test
2016-03-25 14:05:52 -07:00
7f8f138d6a
fix addPendingBitWhenPartialWritemask
2016-03-24 20:01:50 -07:00
11bd15432a
fix bug in RTC
2016-03-24 20:01:50 -07:00
00b3908d92
git rid of reorder queue in narrower
2016-03-24 20:01:50 -07:00
8d1ba4d1ec
Remove hard-coded XLEN values from D$
2016-03-24 14:52:12 -07:00
d1639416cb
Merge pull request #77 from ucb-bar/chisel3
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Preliminary Chisel 3 Support
2016-03-24 12:56:36 -07:00
39cf945efb
Use Chisel 3 to build verilog on Travis
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Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
d697559754
Correct the polarity of the non-backup-memory HTIF
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This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
7d5eac189b
Bump the uncore for some Chisel3 fixes
2016-03-24 12:00:13 -07:00
4744deec28
Fix the SCR file for Chisel 3
2016-03-24 12:00:13 -07:00
476db6ef39
Move to a newer Scala version
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Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
c6e974b110
Merge pull request #30 from ucb-bar/chisel3
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Chisel 3 support
2016-03-24 11:52:02 -07:00
471f4c2695
change WriteMaskedPutBlockRegression for better bug detection
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Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
2016-03-23 16:31:19 -07:00
c9e1b72972
Don't assign SInt(-1) to a UInt
2016-03-23 16:24:27 -07:00
3b0e87f42a
pass CSRs through to ground test and get DMA tests working again
2016-03-22 20:18:02 -07:00
7b7e954133
make sure DummyPTW does not invalidate the TLB
2016-03-22 19:59:58 -07:00
6da45e7f26
Trace generator: updates and additions to the scripts directory.
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(1) Introduce tracegen.py, a script that invokes the emulator (built
with TraceGenConfig), sending a SIGTERM once all cores are finished.
(2) Update toaxe.py to gather some statistics about the trace.
(3) Introduce tracestats.py, which displays the stats in a useful way.
(4) Introduce tracegen+check.py, a top-level script that generates
traces, checks them, and emits stats. If this commit is pulled, it
should be done after pulling my latest groundtest commit.
2016-03-21 15:28:15 -07:00
aa22f175c3
Add cloneType methods for Chisel3
2016-03-21 13:35:02 -07:00
c989ec5813
Fix the SCR file for Chisel 3
2016-03-21 11:55:40 -07:00
1344d09cef
Fix the SCR file for Chisel 3
2016-03-21 11:55:18 -07:00
bda5772e98
Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too.
2016-03-18 12:11:11 +00:00
c13b8d243d
BroadcastHub race on allocating VolWBs vs Acquires
2016-03-17 18:32:35 -07:00
5f3d3a0b2d
Bugfix for probe flags in L2BroadcastHub
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Closes #25
2016-03-17 16:42:40 -07:00
49d82864bf
Fix StoreDataQueue allocation bug in BroadcastHub
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Closes #27
2016-03-17 12:31:18 -07:00
b5992186df
include top-level makefrag in regressions
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fixes issue with rocketchip_addons inclusion
2016-03-16 15:52:28 -07:00
e90a9dfb2b
make taking max of multiple integers in config a bit easier
2016-03-16 14:35:08 -07:00
4fc2a14a63
Fix MIF bug that cuts off upper xact id bits
2016-03-16 13:50:30 -07:00
8a47c3f346
Make sure there's enough xact id bits
2016-03-16 13:49:30 -07:00
04be438847
Avoid conflicting assigments to registers in timers. Give priority to start over stop.
2016-03-16 12:54:19 -07:00
137b77d780
Merge pull request #4 from ucb-bar/chisel3
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Work around Chisel3's lack of 0-width wires
2016-03-15 17:30:34 -07:00
50f61687de
Work around Chisel3's lack of 0-width wires
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This is super ugly, but it's necessary to get Chisel3 to compile. Note
that this still fails simulations in Chisel3, so it might be wrong.
2016-03-14 22:50:37 -07:00
9dc0cbdfa4
WIP on privileged spec v1.9
2016-03-14 18:03:33 -07:00
13dcb96b7f
Update TLB interface
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n.b. no need to set mprv, since prv = S.
2016-03-14 17:55:19 -07:00
648437e7cb
Merge pull request #70 from ucb-bar/add-rv32-support
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Add RV32 test/configuration options
2016-03-14 17:06:39 -07:00
db09f310a1
Define MIFMasterTagBits as # bits a master can *use* in tag
2016-03-11 16:48:13 -08:00
f2ded2721d
Merge branch 'master' into add-rv32-support
2016-03-10 19:33:04 -08:00
