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Author SHA1 Message Date
Andrew Waterman 890528c641 Avoid data corruption under correctable tag error during flush 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 16:09:44 -08:00
Andrew Waterman 34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" 
This reverts commit 44eb4d12b5.
 2017-11-29 16:09:30 -08:00
Andrew Waterman 44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 09:42:00 -08:00
Megan Wachs f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Andrew Waterman 5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127) 
Firrtl can't DCE it because it would require analyzing the state machine.
 2017-11-22 18:40:02 -06:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra 3b299397db diplomacy: bind resources to outer-most binding 
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra 44f99cd9a5 diplomacy: eliminate redundant bindings 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
Yunsup Lee a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00
Andrew Waterman 5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption 
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db066303b.
 2017-11-20 12:30:40 -08:00
Andrew Waterman 66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" 
This reverts commit 3db066303b.
 2017-11-20 12:26:04 -08:00
Wesley W. Terpstra ec809483b0 BusBypass: assert fail if the widths of the two slaves do not match 2017-11-18 14:37:27 -08:00
Wesley W. Terpstra c475c78c2f BusBlocker: don't provide an (incorrect) default value for width 2017-11-18 14:33:00 -08:00
Wesley W. Terpstra 7a1937242a coreplex: provide correct bus-width for ITIM blockers 2017-11-18 14:32:37 -08:00
Henry Cook f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry Cook b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Megan Wachs e7704f46c8
Add some add'l debug features (#1112) 
* debug: Update macros from spec

* debug: some corrections in the auto-generated files

* debug: update renamed fields

* Debug: implement the implicit ebreak option for small program buffers

* debug: clean up some unused code and add more require() explanations

* debug: make implicit ebreak false

* debug: Add the havereset/haveresetack functionality

* debug: program buffer can still be 16 even if there is an implicit ebreak
 2017-11-16 17:14:41 -08:00
Wesley W. Terpstra 61ef560c75
tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111) 2017-11-14 17:49:10 -08:00
Wesley W. Terpstra 8b79f0394e
Merge pull request #1105 from freechipsproject/axi4-xbar 
axi4: add an Xbar
 2017-11-14 16:18:23 -08:00
Wesley W. Terpstra 509a48c9c9
TLToAXI4: block TL early source re-use before it goes to AXI4 (#1110) 
This is a follow-up to PR #1108.

Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
 2017-11-14 16:08:43 -08:00
Wesley W. Terpstra e370934c50 AXI4Xbar: reduce number of special cases 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 9004ecdf25 unittest: include AXI4Xbar in regression 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 5875017956 axi4: add an Xbar 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 72c89f7e30 axi4: add a Filter suitable for manipulating test visibility 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra bfc0ba679a axi4: add a Delayer for unit tests 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 1902ba063a Filter: can claim to be out-of-order when you are not 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 58a93e2100 AXI4SRAM: handy helper object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 353ddffc11 RAMModel: add a convenience object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 147fad6387
Fix AXI4 FIFO ordering for masters with early source reuse (#1108) 
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
 2017-11-13 20:32:09 -08:00
Henry Cook 7098ebf439
rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Wesley W. Terpstra 0cfa801bfc
coreplex: allow MMIO to be misaligned (#1103) 2017-11-10 15:12:28 -08:00
Wesley W. Terpstra a061b16ee3
coreplex: fix typo (#1104) 2017-11-10 15:11:56 -08:00
Andrew Waterman 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman efdb418559
Merge pull request #1098 from freechipsproject/frontend 
Frontend improvements
 2017-11-09 17:44:38 -08:00
Andrew Waterman d0c6cbba6b Improve frontend branch prediction 
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
 2017-11-09 00:00:56 -08:00
Andrew Waterman bb9d8264e2 "Correct" ITIM uncorrectable errors 
This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors.  Previously, another core had to do it.
 2017-11-08 22:15:03 -08:00
Andrew Waterman 5c1b34d854 Don't report a TL error if overwriting a whole ITIM word 2017-11-08 22:15:03 -08:00
Andrew Waterman 9b16d25861 Fix reporting of ITIM error addresses on slave-port accesses 2017-11-08 22:15:03 -08:00
Wesley W. Terpstra b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls (#1095) 
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
 2017-11-08 15:31:19 -08:00
Andrew Waterman 4514adb77c
Merge pull request #1093 from freechipsproject/local-error-interrupt 
generate local interrupts on bus/ecc errors
 2017-11-07 14:19:53 -08:00
Henry Cook d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Andrew Waterman 34f38b0fb1 Don't permit vectoring of high interrupts 
Send them to the base of the vector to obviate an adder
 2017-11-07 01:59:30 -08:00
Andrew Waterman 6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts 2017-11-06 18:03:59 -08:00
Andrew Waterman be3a3e0187 Generate local interrupt #128 on bus errors 
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
 2017-11-06 18:03:59 -08:00
Andrew Waterman ac096a89e7 Make BusErrorUnit support 32-bit stores 
Otherwise it isn't too useful for RV32!
 2017-11-06 18:03:59 -08:00
Andrew Waterman 6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt 2017-11-06 18:03:59 -08:00
Andrew Waterman bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1 
Don't emit PTW covers when !usingVM
 2017-11-06 18:03:36 -08:00
Andrew Waterman 95d00b13cc Report ITIM slave port errors to BusErrorUnit 2017-11-06 12:39:17 -08:00
Andrew Waterman c84848afa6 Report ITIM uncorrectable errors over D-channel 2017-11-06 12:32:45 -08:00
Wesley W. Terpstra 7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test 2017-11-06 12:05:44 -08:00
Wesley W. Terpstra 88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns 2017-11-06 11:53:09 -08:00
Wesley W. Terpstra 25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error 2017-11-06 11:31:23 -08:00
Wesley W. Terpstra dcf67b49fa
BusBypass: only stall A once the last beat is accepted (#1090) 
When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
 2017-11-06 11:13:15 -08:00
Andrew Waterman 989eeb78f9 Prevent some unnecessary pipeline replays 2017-11-06 11:04:06 -08:00
Andrew Waterman c8bc487ab8 Use pseudo-LRU policy in BTB 
FIFO falls on its face if the working set doesn't fit in the BTB.
 2017-11-03 16:27:04 -07:00
Andrew Waterman f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Andrew Waterman 7bef935d2a
Don't emit PTW covers when !usingVM 2017-11-03 15:03:27 -07:00
Wesley W. Terpstra 16116991e7
Fix stateless caching (#1084) 
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
 2017-11-01 11:05:56 -07:00
Wesley W. Terpstra 4ccdbecb63
Async covers (#1085) 
* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic
 2017-11-01 11:03:45 -07:00
Andrew Waterman a2b80100e2 Make PseudoLRU policy support non-power-of-2 sizes 2017-11-01 01:47:23 -07:00
Wesley W. Terpstra 84145959e1
tilelink: fix error fragmentation from multibeat to multibeat (#1082) 
Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
 2017-10-31 17:34:46 -07:00
Wesley W. Terpstra 8ec06151b0
interrupts: Crossing should use asynchronously reset registers (#1080) 
Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
 2017-10-31 16:29:06 -07:00
Megan Wachs f86489b59e
JTAG: Use sorted map for stability (#1073) 
* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup
 2017-10-31 15:33:41 -07:00
Andrew Waterman 3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079) 
Workaround: disable interrupts and then do:

.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
 2017-10-31 00:49:56 -07:00
Wesley W. Terpstra 45a904b396 ahb: ignore hrdata on an AHB error 
From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 6318d7d44c ahb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 2912a76a2b axi4: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra e8ed450f13 unit tests: do not use LFSR16 which has a common seed! 
We want each LFSR to generate independent noise.
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra ec70e5fb02 apb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 0280a1f218 tilelink: add the ErrorEvaluator, a test bench error helper 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra d6f1612812 tilelink: ToAHB should make read errors sticky as well 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 0992a459be tilelink: Fragmenter should combine errors 2017-10-30 21:09:42 -07:00
Wesley W. Terpstra 13d0bf6808 tilelink: Monitor now enforces spec-defined error rules 2017-10-30 11:27:07 -07:00
Wesley W. Terpstra a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 6aac658184 diplomacy: convert all helper objects to return nodes 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra eeb11a2693 coreplex: eliminate dead code 2017-10-27 01:13:35 -07:00
Wesley W. Terpstra 9f83db998e tile: don't chain too many unneeded TileLink adapters (#1075) 2017-10-27 01:12:58 -07:00
Wesley W. Terpstra e12bdfdf9b coreplex: attach example external interrupts (#1076) 
Fixes #1071
 2017-10-27 01:12:42 -07:00
Wesley W. Terpstra 13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074) 2017-10-26 23:39:56 -07:00
Wesley W. Terpstra 1d8e539362 coreplex: confirm crossings actually cross the right boundary 2017-10-26 15:53:01 -07:00
Wesley W. Terpstra 60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope 2017-10-26 15:19:05 -07:00
Wesley W. Terpstra a060c37173 diplomacy: expose the API to query a Node for its neighbours 2017-10-26 15:08:06 -07:00
Wesley W. Terpstra e2d6d4d725 diplomacy: eliminate bindings dead-code 2017-10-26 15:02:21 -07:00
Wesley W. Terpstra 9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra 2acff8d21f util: delete old long-deprecated crossing code 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra da7703aee9 crossings: deprecate non-island crossing style 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra 76df1397e0 crossings: stop using deprecated APIs in tests 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 380cc6f03b axi4: now also supports the island pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra ce2b904b19 coreplex: tidy up interrupt crossings 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra e30906589f coreplex: refactor crossings to use node pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 6276ea4291 diplomacy: it possible for NodeHandles to put indirection on their attachment 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 8c5e8dd071 coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra e894d64bca diplomacy: support := composition 
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...

It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
 2017-10-26 13:04:32 -07:00
Henry Cook b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry Cook 9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry Cook 95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 2175758050 interrupts: implement in crossing wrapper 2017-10-26 13:04:29 -07:00
Wesley W. Terpstra c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Wesley W. Terpstra 6bc9c9fc6c coreplex: add a crossing wrapper to generalize the island pattern 2017-10-25 16:56:50 -07:00
Wesley W. Terpstra 7453186b59 diplomacy: add reflection for parent modules to nodes 2017-10-25 16:56:50 -07:00
Christopher Celio c4978712c9 csr: allow for superscalar decode (#1069) 
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
 2017-10-25 13:58:26 -07:00
Wesley W. Terpstra 82b1aa8116 coreplex: print the A first to look nicer 2017-10-18 16:52:35 -07:00
Wesley W. Terpstra a1ac23d7ec coreplex: continue to print the device name in the address map 2017-10-18 16:44:53 -07:00
Richard Xia 5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Megan Wachs e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Henry Cook 1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Wesley W. Terpstra 8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) 
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
 2017-10-12 16:41:54 -07:00
Andrew Waterman 21b5367259 Expand C.UNIMP correctly (#1052) 
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
 2017-10-12 14:00:14 -07:00
Henry Cook ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry Cook ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Wesley W. Terpstra f82e441426 axi4: implement a diplomatic AXI4 clock crossing (#1049) 2017-10-12 00:05:45 -07:00
Henry Cook 66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Megan Wachs 7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Henry Cook 60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook 2dbe882e58 tilelink: add BasicBusBlocker device 2017-10-11 13:36:42 -07:00
Henry Cook 9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice 2017-10-11 12:45:36 -07:00
Henry Cook ec056535dc tilelink: add DeadlockDevice 2017-10-11 12:44:23 -07:00
Wesley W. Terpstra b566ffedea system: fix DefaultFPGAConfig (#1047) 
It was missing cores. Fixes #736.
 2017-10-11 10:48:41 -07:00
Henry Cook 329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook 1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Wesley W. Terpstra 5d62c321f4 generator: create annotation file 2017-10-10 23:23:06 -07:00
Henry Cook 75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Wesley W. Terpstra b3bdf5eca6 RegField: default argument for .bytes 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra e094b94ce5 clint: use RegField.toBytes to save some work 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra 10472b4296 diplomacy: auto connect bundles in a stable order (#1045) 2017-10-10 19:41:46 -07:00
Henry Cook 1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Andrew Waterman b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) 2017-10-10 17:14:33 -07:00
Henry Cook 37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook 660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Andrew Waterman 50429daef4 Merge pull request #1036 from freechipsproject/l1-cover 
Add some covers for L1 memory system
 2017-10-10 12:28:48 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Wesley W. Terpstra d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman 1474ab438d Remove extraneous signal 2017-10-09 18:33:50 -07:00
Andrew Waterman f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Andrew Waterman 2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Megan Wachs 0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs 0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs 9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Andrew Waterman 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman a0e5a20b60 Don't route branch comparison result through ALU output mux 
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
 2017-10-07 17:36:24 -07:00
Andrew Waterman 36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Wesley W. Terpstra bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030) 
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
 2017-10-05 12:49:49 -07:00
Wei Song (宋威) 81b9ac42a3 add comments to diplomacy resource. (#913) 2017-10-05 12:45:56 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Andrew Waterman 5a84564203 Merge pull request #1023 from freechipsproject/csr-cleanup 
Generalize CSR file to support simpler cores
 2017-10-04 14:04:59 -07:00
Andrew Waterman 32fda51a2c Get rid of paddrBits from SystemBus (#1029) 2017-10-04 12:11:37 -07:00
Andrew Waterman 7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend 
It is more generally useful.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 2786e42d99 Don't register interrupts in CSRFile 
They are usually registered outside the tile in a CDC.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman 09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Henry Cook 5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid 
Make use of the new DontTouch annotation
 2017-10-03 12:55:34 -07:00
Henry Cook d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Henry Cook cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire 
which contains hartid.
 2017-10-02 19:36:10 -07:00
Wesley W. Terpstra a2dc13669a Error grants (#1025) 
* CacheCork: an error Grant still says 'toT' even though it is transient

Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.

This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.

* Error: handle permissions properly
 2017-10-02 14:49:25 -07:00
Megan Wachs 9c9cb68462 JTAG Coverage: Add reset coverage points 2017-10-02 11:08:13 -07:00
Megan Wachs a8ab06d572 JTAG: Add coverage points to the JTAG Tap 2017-10-02 11:08:13 -07:00
Jack Koenig 8891bf1b64 Bump chisel3 and firrtl, update plugin versions 
And update chisel3 code
 2017-09-29 15:44:27 -07:00
Henry Cook 547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Andrew Waterman 9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn 
Provide correct trace insn on interrupts when possible
 2017-09-27 18:47:24 -07:00
Andrew Waterman 9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Wesley W. Terpstra 0a287df0f7 Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles 2017-09-27 16:28:10 -07:00
Andrew Waterman 31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Wesley W. Terpstra feae216f05 clint: output interrupts in the correct direction 2017-09-27 15:18:42 -07:00
Henry Cook 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook 652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Wesley W. Terpstra 9307092d14 coreplex: draw the FrontBus at the bottom and SystemBus at the top 2017-09-27 14:20:39 -07:00
Henry Cook f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Andrew Waterman 78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Wesley W. Terpstra e07d86aecd rocket: flip interrupt rendering so cores are on top 2017-09-27 12:46:29 -07:00
Andrew Waterman 583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra 1fda05970a rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:33:08 -07:00
Wesley W. Terpstra ce01ab2700 RegisterRouter: correctly create interrupts vector 2017-09-27 12:27:16 -07:00
Wesley W. Terpstra 0268959c24 rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:02:04 -07:00
Wesley W. Terpstra e35d3df6ea diplomacy: detect and report cycles in the diplomatic graph 2017-09-27 11:46:06 -07:00
Wesley W. Terpstra 5af08966d8 coreplex: fix WithoutTLMonitors 
closes #1017
 2017-09-27 00:57:18 -07:00
Wesley W. Terpstra d87536ff8b diplomacy: make NodeHandle recursively composable 2017-09-26 18:47:16 -07:00
Wesley W. Terpstra 31a934bec0 coreplex: buses are now LazyModules with LazyScope 2017-09-26 14:58:56 -07:00
Wesley W. Terpstra da40573a64 diplomacy: replace LazyModule.stack with an optional scope 2017-09-26 14:56:50 -07:00
Wesley W. Terpstra a2b423d647 diplomacy: add LazyScope to post-hoc add children to a LazyModule 2017-09-26 14:40:45 -07:00
Wesley W. Terpstra a27e853101 diplomacy: move rendering properties to edges 
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
 2017-09-26 13:24:36 -07:00
Wesley W. Terpstra 76c2aa1661 diplomacy: introduce the typing-saving SimpleNodeImp 2017-09-26 12:28:59 -07:00
Wesley W. Terpstra 870ed3d219 diplomacy: fix the order of auto signals 2017-09-26 11:56:55 -07:00
Wesley W. Terpstra d22ec1eddf diplomacy: beautify node signal prefixes 2017-09-26 11:56:53 -07:00
Henry Cook 9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
Wesley W. Terpstra fef5054cec diplomacy: disambiguate names only when necessary 
If two (or more) 'auto_' things have the same name, append _0 and _1 to them.

The order of definitions is unaffected; ie:
  a => a_0
  b => b_0
  b => b_1
  c => c
  a => a_1
 2017-09-25 16:12:34 -07:00
Wesley W. Terpstra 5323cf88dd util: add Option.unzip 2017-09-25 12:06:31 -07:00
Wesley W. Terpstra 60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra bc225a4e82 diplomacy: place Monitors inside LazyModules sinks 
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.

Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
 2017-09-22 23:36:17 -07:00
Wesley W. Terpstra cfb7f13408 diplomacy: capture SourceInfo at point of := in Edge parameters 2017-09-22 22:25:56 -07:00
Wesley W. Terpstra 16969eb1f6 diplomacy: spelling fix 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra 9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra 53f6999ea8 Splitter: reuse TLCustom node instead of special diplomacy case 2017-09-22 14:58:39 -07:00
Wesley W. Terpstra 6fa5250e1f config: fix warning 2017-09-22 14:58:36 -07:00
Wesley W. Terpstra 17ba209ed0 coreplex: name LazyModules 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra 1fedabcb55 tilelink: invoke LazyModule() at point of monitor binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra dfc815f4d3 rocket: invoke LazyModule at point of use/binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra 87d597c70d ahb apb: remove unintentional var 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra 3656e975a1 diplomacy: ValName captures val bindings for Nodes 2017-09-22 14:38:47 -07:00
Henry Cook 81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook 28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman 88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman 6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman 9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman 026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman 5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman dbf599f6a1 Support SynchronizerShiftReg(sync = 0) 
This makes it easier to parameterize code where the synchronizer
might not always be needed.
 2017-09-20 00:05:07 -07:00
Andrew Waterman 79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 9a175b0fb1 Statically report error correction/detection capability from ECC codes 2017-09-20 00:05:07 -07:00
Andrew Waterman 4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Andrew Waterman acea94bcef Merge pull request #1001 from freechipsproject/address-decoder 
Address decoder "improvements"
 2017-09-19 22:38:53 -07:00
Jacob Chang b4fc5104d4 Add cover property API that can be refined through Config PropertyLibrary (#998) 2017-09-19 19:26:54 -07:00
Henry Cook 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Andrew Waterman 87b92cb206 Scan AddressDecoder bits left to right 
This heuristic is brittle but fixes deduplication in RocketTile.
 2017-09-19 17:47:24 -07:00
Andrew Waterman 72bd89a2af Add another AddressDecoder debug message 2017-09-19 17:47:17 -07:00
Andrew Waterman fb2ad11347 Improve AddressDecoder optimization function 
This function is better 27% of the time but worse 6% of the time.
 2017-09-19 17:47:12 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00