riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: provide correct bus-width for ITIM blockers

This commit is contained in:
Wesley W. Terpstra 2017-11-18 14:32:37 -08:00
parent 9e0c26f855
commit 7a1937242a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -38,7 +38,7 @@ case class TileSlavePortParams(
(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
val tile_slave_blocker =
blockerCtrlAddr
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes))
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }