rocket-chip/scala at 1902ba063ae208e6a40ccd52cb52ba1f2b01137b - rocket-chip - Tiband Gitea

riscv/rocket-chip

History

Wesley W. Terpstra 1902ba063a Filter: can claim to be out-of-order when you are not

2017-11-14 15:09:09 -08:00

..

AXI4SRAM: handy helper object

2017-11-14 15:09:09 -08:00

config: fix warning

2017-09-22 14:58:36 -07:00

coreplex: allow MMIO to be misaligned (#1103 )

2017-11-10 15:12:28 -08:00

BusBypass: only stall A once the last beat is accepted (#1090 )

2017-11-06 11:13:15 -08:00

diplomacy: define only primary node types

2017-10-28 11:16:56 -07:00

coreplex: leverage improved := composition

2017-10-26 13:04:32 -07:00

interrupts: Crossing should use asynchronously reset registers (#1080 )

2017-10-31 16:29:06 -07:00

JTAG: Use sorted map for stability (#1073 )

2017-10-31 15:33:41 -07:00

RegField: default argument for .bytes

2017-10-10 19:49:35 -07:00

Queue: silence some warnings

2017-11-14 15:09:09 -08:00

coreplex: WithStatelessBridge => WithIncoherentTiles (#1092 )

2017-11-07 13:47:56 -08:00

Provide option to support AMOs only on I/O, not DTIM/D$

2017-11-09 17:45:53 -08:00

Filter: can claim to be out-of-order when you are not

2017-11-14 15:09:09 -08:00

axi4: implement a diplomatic AXI4 clock crossing (#1049 )

2017-10-12 00:05:45 -07:00

Merge pull request #1098 from freechipsproject/frontend

2017-11-09 17:44:38 -08:00