riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Invalidate TL error bit in D$ once progress is made

Browse Source
This commit is contained in:
Andrew Waterman 2017-11-07 00:52:18 -08:00
parent d8d4504995
commit 6176b348dc
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/rocket/DCache.scala
View File

@ -305,6 +305,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
when (lrscCount > 0) { lrscCount := lrscCount - 1 }
when ((s2_valid_masked && lrscCount > 0) || io.cpu.invalidate_lr) { lrscCount := 0 }
when (s2_valid_masked || io.cpu.invalidate_lr) { tl_error_valid := false }
// don't perform data correction if it might clobber a recent store
val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad)