riscv/rocket-chip
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RocketTile: if the dcache is incoherent, report it in DTS

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This commit is contained in:
Wesley W. Terpstra 2017-11-20 17:19:50 -08:00
parent 39f1acfd34
commit baa31edf7d
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/tile/RocketTile.scala
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@ -66,6 +66,9 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
"sifive,itim" -> ofRef(frontend.icache.device))
val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
"sifive,d-cache-incoherent" -> Nil)
val icache = rocketParams.icache.map(i => Map(
"i-cache-block-size" -> ofInt(block),
"i-cache-sets" -> ofInt(i.nSets),
@ -105,7 +108,7 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
"status" -> ofStr("okay"),
"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
"riscv,isa" -> ofStr(isa))
++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
}
}
val intcDevice = new Device {