Wesley W. Terpstra baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS

2017-11-20 17:42:06 -08:00

..

amba

AXI4Xbar: reduce number of special cases

2017-11-14 15:09:09 -08:00

config

config: fix warning

2017-09-22 14:58:36 -07:00

coreplex

coreplex: provide correct bus-width for ITIM blockers

2017-11-18 14:32:37 -08:00

devices

BusBypass: assert fail if the widths of the two slaves do not match

2017-11-18 14:37:27 -08:00

diplomacy

diplomacy: define only primary node types

2017-10-28 11:16:56 -07:00

groundtest

tile: put a BasicBusBlocker inside RocketTile (#1115)

2017-11-17 17:26:48 -08:00

interrupts

interrupts: Crossing should use asynchronously reset registers (#1080)

2017-10-31 16:29:06 -07:00

jtag

JTAG: Use sorted map for stability (#1073)

2017-10-31 15:33:41 -07:00

regmapper

RegField: default argument for .bytes

2017-10-10 19:49:35 -07:00

rocket

icache: add a couple cover points for I$ and ITIM iteraction

2017-11-20 13:14:38 -08:00

system

coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)

2017-11-07 13:47:56 -08:00

tile

RocketTile: if the dcache is incoherent, report it in DTS

2017-11-20 17:42:06 -08:00

tilelink

tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111)

2017-11-14 17:49:10 -08:00

unittest

unittest: include AXI4Xbar in regression

2017-11-14 15:09:09 -08:00

util

Merge pull request #1098 from freechipsproject/frontend

2017-11-09 17:44:38 -08:00