riscv/rocket-chip
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Fix reporting of ITIM error addresses on slave-port accesses

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Andrew Waterman 2017-11-08 16:46:25 -08:00 committed by Wesley W. Terpstra
parent 9441c29d92
commit 9b16d25861
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/ICache.scala
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@ -255,7 +255,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s1_clk_en = s1_valid || s1_slaveValid
val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en)
val s2_hit_way = OHToUInt(s2_tag_hit)
val s2_scratchpad_word_addr = Cat(s2_hit_way, io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
val s2_dout = RegEnable(s1_dout, s1_clk_en)
val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)