axi4: add an Xbar
This commit is contained in:
Wesley W. Terpstra
parent
72c89f7e30
commit
5875017956
@ -21,6 +21,13 @@ object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortPara
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case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams)
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case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams)
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case class AXI4NexusNode(
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masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters,
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slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 999,
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numSlavePorts: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends NexusNode(AXI4Imp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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case class AXI4AdapterNode(
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masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters = { m => m },
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slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters = { s => s },
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320
src/main/scala/amba/axi4/Xbar.scala
Normal file
320
src/main/scala/amba/axi4/Xbar.scala
Normal file
@ -0,0 +1,320 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.unittest._
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import freechips.rocketchip.tilelink._
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class AXI4Xbar(
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arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
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maxFlightPerId: Int = 7,
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awQueueDepth: Int = 2)(implicit p: Parameters) extends LazyModule
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{
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require (maxFlightPerId >= 1)
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require (awQueueDepth >= 1)
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val node = AXI4NexusNode(
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numMasterPorts = 1 to 999,
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numSlavePorts = 1 to 999,
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masterFn = { seq =>
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seq(0).copy(
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userBits = seq.map(_.userBits).max,
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masters = (AXI4Xbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
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port.masters map { master => master.copy(id = master.id.shift(range.start)) }
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}
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)
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},
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slaveFn = { seq =>
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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slaves = seq.flatMap { port =>
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require (port.beatBytes == seq(0).beatBytes,
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s"Xbar data widths don't match: ${port.slaves.map(_.name)} has ${port.beatBytes}B vs ${seq(0).slaves.map(_.name)} has ${seq(0).beatBytes}B")
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port.slaves
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}
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)
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})
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lazy val module = new LazyModuleImp(this) {
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val (io_in, edgesIn) = node.in.unzip
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val (io_out, edgesOut) = node.out.unzip
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// Grab the port ID mapping
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val inputIdRanges = AXI4Xbar.mapInputIds(edgesIn.map(_.master))
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// Find a good mask for address decoding
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val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
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val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
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// To route W we need to record where the AWs went
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val awIn = Seq.fill(io_in .size) { Module(new Queue(UInt(width = io_out.size), awQueueDepth, flow = true)) }
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val awOut = Seq.fill(io_out.size) { Module(new Queue(UInt(width = io_in .size), awQueueDepth, flow = true)) }
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val requestARIO = Vec(io_in.map { i => Vec(outputPorts.map { o => o(i.ar.bits.addr) }) })
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val requestAWIO = Vec(io_in.map { i => Vec(outputPorts.map { o => o(i.aw.bits.addr) }) })
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val requestROI = Vec(io_out.map { o => Vec(inputIdRanges.map { i => i.contains(o.r.bits.id) }) })
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val requestBOI = Vec(io_out.map { o => Vec(inputIdRanges.map { i => i.contains(o.b.bits.id) }) })
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// W follows the path dictated by the AW Q
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for (i <- 0 until io_in.size) { awIn(i).io.enq.bits := requestAWIO(i).asUInt }
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val requestWIO = Vec(awIn.map { q => if (io_out.size > 1) Vec(q.io.deq.bits.toBools) else Vec.fill(1){Bool(true)} })
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = AXI4BundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
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// Transform input bundles
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val in = Wire(Vec(io_in.size, AXI4Bundle(wide_bundle)))
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for (i <- 0 until in.size) {
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in(i) <> io_in(i)
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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// Manipulate the AXI IDs to differentiate masters
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val r = inputIdRanges(i)
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in(i).aw.bits.id := io_in(i).aw.bits.id | UInt(r.start)
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in(i).ar.bits.id := io_in(i).ar.bits.id | UInt(r.start)
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io_in(i).r.bits.id := trim(in(i).r.bits.id, r.size)
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io_in(i).b.bits.id := trim(in(i).b.bits.id, r.size)
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if (io_out.size > 1) {
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// Block A[RW] if we switch ports, to ensure responses stay ordered (also: beware the dining philosophers)
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val endId = edgesIn(i).master.endId
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val arFIFOMap = Wire(init = Vec.fill(endId) { Bool(true) })
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val awFIFOMap = Wire(init = Vec.fill(endId) { Bool(true) })
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val arSel = UIntToOH(io_in(i).ar.bits.id, endId)
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val awSel = UIntToOH(io_in(i).aw.bits.id, endId)
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val rSel = UIntToOH(io_in(i).r .bits.id, endId)
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val bSel = UIntToOH(io_in(i).b .bits.id, endId)
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val arTag = OHToUInt(requestARIO(i).asUInt, io_out.size)
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val awTag = OHToUInt(requestAWIO(i).asUInt, io_out.size)
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for (master <- edgesIn(i).master.masters) {
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def idTracker(port: UInt, req_fire: Bool, resp_fire: Bool) = {
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if (master.maxFlight == Some(1)) {
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// No need to worry about response order if at most 1 request possible
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Bool(true)
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} else if (maxFlightPerId == 1) {
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// No need to track where it went if we cap it at 1 request
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val allow = RegInit(Bool(true))
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when (req_fire) { allow := Bool(false) }
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when (resp_fire) { allow := Bool(true) }
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allow
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} else {
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val legalFlight = master.maxFlight.getOrElse(maxFlightPerId+1)
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val flight = legalFlight min maxFlightPerId
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val canOverflow = legalFlight > flight
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val count = RegInit(UInt(0, width = log2Ceil(flight+1)))
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val last = Reg(UInt(width = log2Ceil(io_out.size)))
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count := count + req_fire.asUInt - resp_fire.asUInt
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assert (!resp_fire || count =/= UInt(0))
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assert (!req_fire || count =/= UInt(flight))
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when (req_fire) { last := port }
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(count === UInt(0) || last === port) && (Bool(!canOverflow) || count =/= UInt(flight))
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}
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}
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for (id <- master.id.start until master.id.end) {
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arFIFOMap(id) := idTracker(
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arTag,
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arSel(id) && io_in(i).ar.fire(),
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rSel(id) && io_in(i).r.fire() && io_in(i).r.bits.last)
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awFIFOMap(id) := idTracker(
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awTag,
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awSel(id) && io_in(i).aw.fire(),
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bSel(id) && io_in(i).b.fire())
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}
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}
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val allowAR = arFIFOMap(io_in(i).ar.bits.id)
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in(i).ar.valid := io_in(i).ar.valid && allowAR
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io_in(i).ar.ready := in(i).ar.ready && allowAR
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// Keep in mind that slaves may do this: awready := wvalid, wready := awvalid
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// To not cause a loop, we cannot have: wvalid := awready
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// Block AW if we cannot record the W destination
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val allowAW = awFIFOMap(io_in(i).aw.bits.id)
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val latched = RegInit(Bool(false)) // cut awIn(i).enq.valid from awready
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in(i).aw.valid := io_in(i).aw.valid && (latched || awIn(i).io.enq.ready) && allowAW
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io_in(i).aw.ready := in(i).aw.ready && (latched || awIn(i).io.enq.ready) && allowAW
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awIn(i).io.enq.valid := io_in(i).aw.valid && !latched
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when (awIn(i).io.enq.fire()) { latched := Bool(true) }
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when (in(i).aw.fire()) { latched := Bool(false) }
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// Block W if we do not have an AW destination
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in(i).w.valid := io_in(i).w.valid && awIn(i).io.deq.valid // depends on awvalid (but not awready)
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io_in(i).w.ready := in(i).w.ready && awIn(i).io.deq.valid
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awIn(i).io.deq.ready := io_in(i).w.valid && io_in(i).w.bits.last && in(i).w.ready
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}
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}
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// Transform output bundles
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val out = Wire(Vec(io_out.size, AXI4Bundle(wide_bundle)))
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for (i <- 0 until out.size) {
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io_out(i) <> out(i)
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if (io_in.size > 1) {
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// Block AW if we cannot record the W source
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val latched = RegInit(Bool(false)) // cut awOut(i).enq.valid from awready
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io_out(i).aw.valid := out(i).aw.valid && (latched || awOut(i).io.enq.ready)
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out(i).aw.ready := io_out(i).aw.ready && (latched || awOut(i).io.enq.ready)
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awOut(i).io.enq.valid := out(i).aw.valid && !latched
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when (awOut(i).io.enq.fire()) { latched := Bool(true) }
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when (out(i).aw.fire()) { latched := Bool(false) }
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// Block W if we do not have an AW source
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io_out(i).w.valid := out(i).w.valid && awOut(i).io.deq.valid // depends on awvalid (but not awready)
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out(i).w.ready := io_out(i).w.ready && awOut(i).io.deq.valid
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awOut(i).io.deq.ready := out(i).w.valid && out(i).w.bits.last && io_out(i).w.ready
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}
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}
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// Fanout the input sources to the output sinks
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def transpose[T](x: Seq[Seq[T]]) = Seq.tabulate(x(0).size) { i => Seq.tabulate(x.size) { j => x(j)(i) } }
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val portsAROI = transpose((in zip requestARIO) map { case (i, r) => AXI4Xbar.fanout(i.ar, r) })
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val portsAWOI = transpose((in zip requestAWIO) map { case (i, r) => AXI4Xbar.fanout(i.aw, r) })
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val portsWOI = transpose((in zip requestWIO) map { case (i, r) => AXI4Xbar.fanout(i.w, r) })
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val portsRIO = transpose((out zip requestROI) map { case (o, r) => AXI4Xbar.fanout(o.r, r) })
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val portsBIO = transpose((out zip requestBOI) map { case (o, r) => AXI4Xbar.fanout(o.b, r) })
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// Arbitrate amongst the sources
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for (o <- 0 until out.size) {
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awOut(o).io.enq.bits := // Record who won AW arbitration to select W
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AXI4Arbiter.returnWinner(arbitrationPolicy)(out(o).aw, portsAWOI(o):_*).asUInt
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AXI4Arbiter(arbitrationPolicy)(out(o).ar, portsAROI(o):_*)
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// W arbitration is informed by the Q, not policy
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out(o).w.valid := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.valid))
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out(o).w.bits := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.bits))
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portsWOI(o).zipWithIndex.map { case (p, i) =>
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if (in.size > 1) {
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p.ready := out(o).w.ready && awOut(o).io.deq.bits(i)
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} else {
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p.ready := out(o).w.ready
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}
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}
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}
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for (i <- 0 until in.size) {
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AXI4Arbiter(arbitrationPolicy)(in(i).r, portsRIO(i):_*)
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AXI4Arbiter(arbitrationPolicy)(in(i).b, portsBIO(i):_*)
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}
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}
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}
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object AXI4Xbar
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{
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def apply(
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arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
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maxFlightPerId: Int = 7,
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awQueueDepth: Int = 2)(implicit p: Parameters) = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth)).node
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def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)).map(_.get)
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// Replicate an input port to each output port
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def fanout[T <: AXI4BundleBase](input: IrrevocableIO[T], select: Seq[Bool]) = {
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val filtered = Wire(Vec(select.size, input))
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for (i <- 0 until select.size) {
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filtered(i).bits := input.bits
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filtered(i).valid := input.valid && select(i)
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}
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input.ready := Mux1H(select, filtered.map(_.ready))
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filtered
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}
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}
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object AXI4Arbiter
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{
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def apply[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*) {
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if (sources.isEmpty) {
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sink.valid := Bool(false)
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} else {
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returnWinner(policy)(sink, sources:_*)
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}
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}
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def returnWinner[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*) = {
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require (!sources.isEmpty)
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// The arbiter is irrevocable; when !idle, repeat last request
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val idle = RegInit(Bool(true))
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// Who wants access to the sink?
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val valids = sources.map(_.valid)
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val anyValid = valids.reduce(_ || _)
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// Arbitrate amongst the requests
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val readys = Vec(policy(valids.size, Cat(valids.reverse), idle).toBools)
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// Which request wins arbitration?
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val winner = Vec((readys zip valids) map { case (r,v) => r&&v })
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// Confirm the policy works properly
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require (readys.size == valids.size)
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// Never two winners
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val prefixOR = winner.scanLeft(Bool(false))(_||_).init
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assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
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// If there was any request, there is a winner
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assert (!anyValid || winner.reduce(_||_))
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// The one-hot source granted access in the previous cycle
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val state = RegInit(Vec.fill(sources.size)(Bool(false)))
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val muxState = Mux(idle, winner, state)
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state := muxState
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// Determine when we go idle
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when (anyValid) { idle := Bool(false) }
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when (sink.fire()) { idle := Bool(true) }
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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(sources zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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}
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} else {
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sources(0).ready := sink.ready
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}
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sink.valid := Mux(idle, anyValid, Mux1H(state, valids))
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sink.bits := Mux1H(muxState, sources.map(_.bits))
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muxState
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}
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}
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class AXI4XbarFuzzTest(name: String, txns: Int, nMasters: Int, nSlaves: Int)(implicit p: Parameters) extends LazyModule
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{
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val xbar = AXI4Xbar()
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val slaveSize = 0x1000
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val masterBandSize = slaveSize >> log2Ceil(nMasters)
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def filter(i: Int) = TLFilter.Mmask(AddressSet(i * masterBandSize, ~BigInt(slaveSize - masterBandSize)))
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val slaves = Seq.tabulate(nSlaves) { i => LazyModule(new AXI4RAM(AddressSet(slaveSize * i, slaveSize-1))) }
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slaves.foreach { s => (s.node
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:= AXI4Fragmenter()
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:= AXI4Buffer(BufferParams.flow)
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:= AXI4Buffer(BufferParams.flow)
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:= AXI4Delayer(0.25)
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:= xbar) }
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val masters = Seq.fill(nMasters) { LazyModule(new TLFuzzer(txns, 4, nOrdered = Some(1))) }
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masters.zipWithIndex.foreach { case (m, i) => (xbar
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:= AXI4Delayer(0.25)
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:= AXI4Deinterleaver(4096)
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:= TLToAXI4()
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:= TLFilter(filter(i))
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:= TLRAMModel(s"${name} Master $i")
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:= m.node) }
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := masters.map(_.module.io.finished).reduce(_ || _)
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}
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}
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class AXI4XbarTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut21 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT21", txns, 2, 1)).module)
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val dut12 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT12", txns, 1, 2)).module)
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val dut22 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT22", txns, 2, 2)).module)
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io.finished := Seq(dut21, dut12, dut22).map(_.io.finished).reduce(_ || _)
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}
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