Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)"
This reverts commit 3db066303b
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@ -225,7 +225,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr) && lineInScratchpad(scratchpadLine(s1s3_slaveAddr)))
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val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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Mux(s3_slaveValid, row(s1s3_slaveAddr),
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Mux(s0_slaveValid, row(s0_slaveAddr),
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