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riscv/rocket-chip
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d096fd206bc0a247e12b4aac9d35862df73b35a0
rocket-chip/src/main/scala
T
History
Henry CookandGitHub d096fd206b coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)
2017-11-07 13:47:56 -08:00
..
amba
ahb: ignore hrdata on an AHB error
2017-10-30 21:09:45 -07:00
config
config: fix warning
2017-09-22 14:58:36 -07:00
coreplex
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)
2017-11-07 13:47:56 -08:00
devices
BusBypass: only stall A once the last beat is accepted (#1090)
2017-11-06 11:13:15 -08:00
diplomacy
diplomacy: define only primary node types
2017-10-28 11:16:56 -07:00
groundtest
coreplex: leverage improved := composition
2017-10-26 13:04:32 -07:00
interrupts
interrupts: Crossing should use asynchronously reset registers (#1080)
2017-10-31 16:29:06 -07:00
jtag
JTAG: Use sorted map for stability (#1073)
2017-10-31 15:33:41 -07:00
regmapper
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
rocket
Merge pull request #1089 from freechipsproject/aswaterman-patch-1
2017-11-06 18:03:36 -08:00
system
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)
2017-11-07 13:47:56 -08:00
tile
diplomacy: define only primary node types
2017-10-28 11:16:56 -07:00
tilelink
tilelink: AtomicAutomata; add errors to the unit test
2017-11-06 12:05:44 -08:00
unittest
axi4: implement a diplomatic AXI4 clock crossing (#1049)
2017-10-12 00:05:45 -07:00
util
Async covers (#1085)
2017-11-01 11:03:45 -07:00
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