coreplex: allow MMIO to be misaligned (#1103)
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@ -86,7 +86,7 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
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private val device = new SimpleBus("mmio", Nil)
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val mmio_axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(params.base, params.size-1)),
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address = AddressSet.misaligned(params.base, params.size),
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resources = device.ranges,
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executable = params.executable,
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supportsWrite = TransferSizes(1, params.maxXferBytes),
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@ -165,7 +165,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
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private val device = new SimpleBus("mmio", Nil)
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val mmio_tl = TLManagerNode(Seq(TLManagerPortParameters(
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managers = Seq(TLManagerParameters(
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address = List(AddressSet(params.base, params.size-1)),
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address = AddressSet.misaligned(params.base, params.size),
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resources = device.ranges,
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executable = params.executable,
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supportsGet = TransferSizes(1, sbus.blockBytes),
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