riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)

Browse Source
This commit is contained in:
Henry Cook 2017-11-07 13:47:56 -08:00 committed by GitHub
parent bdda2cb145
commit d096fd206b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/coreplex/Configs.scala
View File

@ -151,13 +151,13 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* system depends on coherence between channels in any way,
* DO NOT use this configuration.
*/
class WithStatelessBridge extends Config((site, here, up) => {
class WithIncoherentTiles extends Config((site, here, up) => {
case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
r.copy(master = r.master.copy(cork = Some(true)))
}
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
implicit val p = coreplex.p
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
val cc = LazyModule(new TLCacheCork(unsafe = true))
cc.node :*= ww.node
(ww.node, cc.node, () => None)
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)(coreplex.p))
(ww.node, ww.node, () => None)
})
})

3
src/main/scala/system/Configs.scala
View File

@ -65,11 +65,10 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config(
new WithNMemoryChannels(0) ++
new WithStatelessBridge ++
new WithIncoherentTiles ++
new With1TinyCore ++
new BaseConfig)
class BaseFPGAConfig extends Config(new BaseConfig)
class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig)