"Correct" ITIM uncorrectable errors
This permits forward progress when a core wants to handle its own uncorrectable ITIM errors. Previously, another core had to do it.
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@ -302,7 +302,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
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when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
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&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) {
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&& s2_valid && s2_data_decoded.error && !s2_tag_disparity) {
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// handle correctable errors on CPU accesses to the scratchpad.
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// if there is an in-flight slave-port access to the scratchpad,
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// report the a miss but don't correct the error (as there is
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@ -315,7 +315,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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respValid := s2_slaveValid || (respValid && !tl.d.ready)
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val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid)
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when (s2_slaveValid) {
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when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }
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when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true }
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def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
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s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt
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}
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