Wesley W. Terpstra 147fad6387 Fix AXI4 FIFO ordering for masters with early source reuse (#1108) ... * TLToAXI4: fix WaR for single-source FIFO masters * TLToAXI4: fix potential counter overflow => WaR hazard If you have a FIFO master with 2^n-1 sources that performs early source re-use, the old code could potentially break FIFO order.		2017-11-13 20:32:09 -08:00
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amba	ahb: ignore hrdata on an AHB error	2017-10-30 21:09:45 -07:00
config	config: fix warning	2017-09-22 14:58:36 -07:00
coreplex	coreplex: allow MMIO to be misaligned (#1103)	2017-11-10 15:12:28 -08:00
devices	BusBypass: only stall A once the last beat is accepted (#1090)	2017-11-06 11:13:15 -08:00
diplomacy	diplomacy: define only primary node types	2017-10-28 11:16:56 -07:00
groundtest	coreplex: leverage improved := composition	2017-10-26 13:04:32 -07:00
interrupts	interrupts: Crossing should use asynchronously reset registers (#1080)	2017-10-31 16:29:06 -07:00
jtag	JTAG: Use sorted map for stability (#1073)	2017-10-31 15:33:41 -07:00
regmapper	RegField: default argument for .bytes	2017-10-10 19:49:35 -07:00
rocket	rocket: fix itim GetPropertyByHartId (#1109)	2017-11-13 19:25:20 -08:00
system	coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)	2017-11-07 13:47:56 -08:00
tile	Provide option to support AMOs only on I/O, not DTIM/D$	2017-11-09 17:45:53 -08:00
tilelink	Fix AXI4 FIFO ordering for masters with early source reuse (#1108)	2017-11-13 20:32:09 -08:00
unittest	axi4: implement a diplomatic AXI4 clock crossing (#1049)	2017-10-12 00:05:45 -07:00
util	Merge pull request #1098 from freechipsproject/frontend	2017-11-09 17:44:38 -08:00