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2359 Commits

Author SHA1 Message Date
Klemens Schölhorn 8710fe9561 Add WithClockFrequency class to update frequencies 2018-06-06 01:04:47 +02:00
Klemens Schölhorn 81d631a6a1 Add small rocket config with fpu and mmu 
This is required for booting linux. The caches are still as small as
in the small core config, so performance will not be great.
 2018-05-19 18:56:56 +02:00
Wesley W. Terpstra 4ba8acb4aa
TLRAM: add support for ECC (#1304) 2018-03-22 14:27:43 -07:00
Henry Cook 12583af4a8
buswrapper: remove buffer chains from api (#1303) 
Just take a single BufferParams for all couplers.
Add TLBuffer.chain in the thunk if you need it.
Preserves default bufferings.
 2018-03-21 23:44:05 -07:00
Andrew Waterman 4cfae27efd
Implement Hauser misa.C misalignment proposal (#1301) 
See 0472bcdd16

- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked in decode
 2018-03-21 23:42:01 -07:00
Wesley W. Terpstra 7f96da2288
ECC: support poison during encode (#1166) 
This makes it possible to update an ECC-protected word while
retaining the fact that the value has an ECC error.
 2018-03-21 16:29:24 -07:00
Henry Cook 7593baf2aa
Merge pull request #1299 from freechipsproject/serializable-metadata 
Store metadata in serializable case classes
 2018-03-21 11:58:05 -07:00
Henry Cook f48c2767d7
subsytem: change front bus buffer defaults (#1300) 2018-03-21 11:56:22 -07:00
Megan Wachs 894960678c
Update Debug Module registers (#1296) 
* Debug: update versions of the files generated from the spec, mostly to get new SBA registers

* Debug: Clean up Halt Summary to use new terminology

* Debug: correct the address of HALTSUM1

* Debug: use simpler expression for numHaltedStatus

* Debug: remove now defunct haltStatus addr
 2018-03-20 14:01:22 -07:00
Henry Cook 70895b6ffa rocket: make RocketTileParams trivial to serialize 
By storing ECC setting as Option[String] and converting it
to a scala Code class later.
 2018-03-20 11:25:02 -07:00
Henry Cook 12997a644d tilelink: TLToAXI4IdMapEntry 2018-03-20 11:24:46 -07:00
Henry Cook 3cb9e57b5e diplomacy: AddressMapEntry and BindingScope.collect 2018-03-20 11:24:41 -07:00
John Wright 9a56e44e32 Fix typo in RAMModel Get printf (#1293) 2018-03-19 11:30:41 -07:00
Andrew Waterman d6bc9c53f0
Save a little power during reset by not writing D$ tags (#1287) 2018-03-15 19:23:09 -05:00
Megan Wachs 4e11491531 Merge remote-tracking branch 'origin/master' into ipxact_descs 2018-03-13 09:26:47 -07:00
Megan Wachs d00a0bba32 Revert "Debug: don't need to fully populate flags array" 
This reverts commit 197699b93a.
 2018-03-12 21:29:55 -07:00
Henry Cook 59d5e61366 regmapper: refactor how json is emitted 2018-03-12 08:24:36 -07:00
Henry Cook ea89259dd4 RegFieldDesc: reserved omits () 2018-03-12 08:24:36 -07:00
Megan Wachs 15e058e3da RegFieldDesc: change how reserved is indicated 2018-03-12 08:24:36 -07:00
Megan Wachs d889a0ca16 RegFieldDesc: add volatile to cause reg in BUE 2018-03-12 08:24:36 -07:00
Megan Wachs e0c3c63826 RegFieldDesc: Update the .bytes method to emit reserved register fields 
instead of applying the same description to the registers that it doesn't
actually do anything with (the padding registers)
 2018-03-12 08:24:36 -07:00
Megan Wachs 0fcacd37df RegFieldDesc: mark some more registers as volatile 2018-03-12 08:24:36 -07:00
Megan Wachs 7458378a4a RegFieldDesc: Update reg field descs to be more correct for devices. 2018-03-12 08:24:36 -07:00
Megan Wachs 3063fd1b46 RegFieldDesc: update DescribedReg to suppot new features 2018-03-12 08:24:36 -07:00
Megan Wachs 2f239f2a9a RegFieldDesc: Add more features to support more IP-XACT like descriptions & emit them in the JSON 2018-03-12 08:24:36 -07:00
Henry Cook 0e0963d360 util: use chisel3.core.dontTouch 2018-03-10 17:04:46 -08:00
Henry Cook 1b93b27da4 util: restore dontTouch annotation; Chisel's is broken on 0 element Aggregates 2018-03-08 16:12:15 -08:00
Henry Cook d6e2c1a73f more != wire deprecations 2018-03-08 12:36:51 -08:00
Megan Wachs 15dc7f6760 JTAGVPI: remove it from Chisel as it is unused 2018-03-07 10:55:45 -08:00
Jack Koenig 64b707cbb6 Bump Chisel and FIRRTL for annotations refactor (#1261) 
Also brings in an autoclonetype enhancement and some bug fixes
 2018-03-07 10:22:38 -08:00
Schuyler Eldridge d0b46c5b8f Align RoCCIO with new cloneType (#1270) 
- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-03-06 17:53:51 -08:00
Megan Wachs f1bd9c99aa
Merge pull request #1262 from freechipsproject/beu-regfield 
Add BusErrorUnit RegFieldDesc
 2018-03-06 12:31:00 -08:00
Megan Wachs f00e9576e3
Merge pull request #1263 from freechipsproject/sim_jtag_reset 
SimJTAG: make the reset/init connectivity more flexible.
 2018-03-06 11:28:51 -08:00
Megan Wachs b669fb3d6a Merge remote-tracking branch 'origin/master' into beu-regfield 2018-03-06 11:04:17 -08:00
Megan Wachs a3d99e5ba2 DescribedReg: fix some imports 2018-03-06 11:02:10 -08:00
Megan Wachs 8856953905 DescribedReg: move to regmapper 2018-03-05 16:12:14 -08:00
Megan Wachs 4256d99a9b PLIC: priority/threshold are really WARL (RWSPECIAL). Explain why. 2018-03-05 16:10:05 -08:00
Megan Wachs 41d1a62713 PLIC: Update RegFieldDesc to reflect the fact that source 0 isn't like all the others 2018-03-05 15:29:14 -08:00
Megan Wachs bd3a72e585 Merge remote-tracking branch 'origin/master' into sim_jtag_reset 2018-03-05 12:41:39 -08:00
Megan Wachs e3be5db3e6 BUE: more verbose register descriptions 2018-03-05 12:02:42 -08:00
Megan Wachs 878a357a0d RegFieldDesc: Add utilities for generating and describing registers at the same time. 2018-03-05 12:02:42 -08:00
Megan Wachs 5eae81038d SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two 2018-03-02 17:29:17 -08:00
Andrew Waterman 644ba6dafa Add BusErrorUnit RegFieldDesc 2018-03-02 17:25:13 -08:00
Jack Koenig 8c6e745653
Bump chisel and firrtl (#1232) 
* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
 2018-03-01 15:19:12 -08:00
Henry Cook 20a8876856
Merge pull request #1190 from freechipsproject/bus-api 
BusWrapper API Update
 2018-03-01 01:13:50 -08:00
Megan Wachs cdd2a9227f
Merge pull request #1256 from freechipsproject/json_emit_enums 
RegFieldDesc: Emit enumerations into JSON if they exist
 2018-02-28 11:32:14 -08:00
Megan Wachs d13dc8ac2a RegFieldDesc: Emit enumerations if they exist 2018-02-28 09:42:25 -08:00
Andrew Waterman a48dd575b2
Merge pull request #1254 from freechipsproject/amo-aqrl 
Fix mapping of acquire/release AMOs to fence operations
 2018-02-27 19:49:40 -06:00
bipult 47d63d6baa
Merge pull request #1251 from freechipsproject/rocket_covers 
Added functional covers
 2018-02-25 09:01:33 -08:00
Andrew Waterman eb6e192ec0 Fix mapping of acquire/release AMOs to fence operations 
AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO.  These had been swapped.  This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).

Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations.  For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
 2018-02-23 16:39:47 -08:00