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rocket-chip/src/main/scala
Andrew Waterman d0c6cbba6b Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
2017-11-09 00:00:56 -08:00
..
amba ahb: ignore hrdata on an AHB error 2017-10-30 21:09:45 -07:00
config config: fix warning 2017-09-22 14:58:36 -07:00
coreplex diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
devices JTAG: Use sorted map for stability (#1073) 2017-10-31 15:33:41 -07:00
diplomacy diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
groundtest coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
interrupts interrupts: Crossing should use asynchronously reset registers (#1080) 2017-10-31 16:29:06 -07:00
jtag JTAG: Use sorted map for stability (#1073) 2017-10-31 15:33:41 -07:00
regmapper RegField: default argument for .bytes 2017-10-10 19:49:35 -07:00
rocket Improve frontend branch prediction 2017-11-09 00:00:56 -08:00
system Merge pull request #1039 from freechipsproject/tile-crossing-params 2017-10-11 17:12:03 -07:00
tile Improve frontend branch prediction 2017-11-09 00:00:56 -08:00
tilelink tilelink: fix error fragmentation from multibeat to multibeat (#1082) 2017-10-31 17:34:46 -07:00
unittest axi4: implement a diplomatic AXI4 clock crossing (#1049) 2017-10-12 00:05:45 -07:00
util Make PseudoLRU policy support non-power-of-2 sizes 2017-11-01 01:47:23 -07:00