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Add clock generation for the mig

This commit is contained in:
Klemens Schölhorn 2018-05-10 01:04:52 +02:00
parent 589e9960c0
commit 77694a6741
2 changed files with 42 additions and 3 deletions
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11
src/main/scala/ip/xilinx/Xilinx.scala
View File

@ -114,6 +114,17 @@ class ml507_dvi_clock extends BlackBox {
}
}
class ml507_ddr2_clock extends BlackBox {
val io = new Bundle {
val CLKIN_P_IN = Clock(INPUT)
val CLKIN_N_IN = Clock(INPUT)
val CLK0_OUT = Clock(OUTPUT)
val CLK90_OUT = Clock(OUTPUT)
val CLKDV_OUT = Clock(OUTPUT)
val LOCKED_OUT = Bool(OUTPUT)
}
}
//-------------------------------------------------------------------------
// vc707_sys_clock_mmcm
//-------------------------------------------------------------------------

34
src/main/scala/shell/xilinx/ML507Shell.scala
View File

@ -16,7 +16,7 @@ import sifive.blocks.devices.chiplink._
import sifive.blocks.devices.terminal._
import sifive.fpgashells.devices.xilinx.xilinxml507mig._
import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_dvi_clock, ml507_sys_clock, vc707reset}
import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_ddr2_clock, ml507_dvi_clock, ml507_sys_clock, vc707reset}
//-------------------------------------------------------------------------
// ML507Shell
@ -57,6 +57,10 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// 100Mhz sysclk
val sys_clock = IO(Input(Clock()))
// 200MHz ddrclk
val ddr_clock_p = IO(Input(Clock()))
val ddr_clock_n = IO(Input(Clock()))
// active high async reset
val reset = IO(Input(Bool()))
@ -97,6 +101,12 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
val dvi_clock = Wire(Clock())
val dvi_reset = Wire(Bool())
val ddr_clk0 = Wire(Clock())
val ddr_clk90 = Wire(Clock())
val ddr_clkdiv0 = Wire(Clock())
val ddr_clk_locked = Wire(Bool())
val ddr_reset = Wire(Bool())
val sd_spi_sck = Wire(Bool())
val sd_spi_cs = Wire(Bool())
val sd_spi_dq_i = Wire(Vec(4, Bool()))
@ -126,9 +136,19 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
ml507_dvi_clock.io.CLKIN_IN := sys_clock
dvi_clock := ml507_dvi_clock.io.CLKFX_OUT
// 200 MHz (DDR2 and IDELAY clock)
val ml507_ddr2_clock = Module(new ml507_ddr2_clock)
ml507_ddr2_clock.io.CLKIN_P_IN := ddr_clock_p
ml507_ddr2_clock.io.CLKIN_N_IN := ddr_clock_n
ddr_clk0 := ml507_ddr2_clock.io.CLK0_OUT
ddr_clk90 := ml507_ddr2_clock.io.CLK90_OUT
ddr_clkdiv0 := ml507_ddr2_clock.io.CLKDV_OUT
ddr_clk_locked := ml507_ddr2_clock.io.LOCKED_OUT
// Clocks locked?
clk_locked := ml507_sys_clock.io.LOCKED_OUT &
ml507_dvi_clock.io.LOCKED_OUT
ml507_dvi_clock.io.LOCKED_OUT &
ddr_clk_locked
//-----------------------------------------------------------------------
// System reset
@ -140,7 +160,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
val safe_reset = Module(new vc707reset)
safe_reset.io.areset := do_reset
safe_reset.io.clock1 := dut_clock
safe_reset.io.clock1 := ddr_clk0
ddr_reset := safe_reset.io.reset1
safe_reset.io.clock2 := dut_clock
safe_reset.io.clock3 := dvi_clock
dvi_reset := safe_reset.io.reset3
@ -167,6 +188,13 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
def connectDDRMemory(dut: HasMemoryML507ModuleImp): Unit = {
ddr2 <> dut.ddr2
dut.ddr_sys.clk0 := ddr_clk0
dut.ddr_sys.clk90 := ddr_clk90
dut.ddr_sys.clkdiv0 := ddr_clkdiv0
dut.ddr_sys.clk_locked := ddr_clk_locked
dut.ddr_sys.clk_idelay := ddr_clk0
dut.ddr_sys.reset := ddr_reset
}
//-----------------------------------------------------------------------