Add XilinxML507MIG periphery and connect top level signals
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@ -3,35 +3,37 @@
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package sifive.fpgashells.devices.xilinx.xilinxml507mig
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import chisel3.core.{Input, Output}
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class MemoryML507Params(
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case class XilinxML507MIGParams(
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address: Seq[AddressSet]
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)
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case object MemoryML507Key extends Field[MemoryML507Params]
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class MemoryController extends BlackBox {
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val io = IO(new Bundle {
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val sys = new MemorySysIO
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val ddr2 = new MemoryDDR2IO
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trait HasMemoryML507 { this: BaseSubsystem =>
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val memory = LazyModule(new TLMemoryML507(p(MemoryML507Key)))
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val request_addr = Input(UInt(28.W))
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val request_read = Input(Bool())
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val request_data = Input(UInt(256.W))
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val request_mask = Input(UInt(32.W))
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val request_valid = Input(Bool())
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val request_ready = Output(Bool())
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// The Fragmenter will not fragment messages <= 32 bytes, so all
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// slaves have to support this size. 64 byte specifies the maximum
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// supported transfer size that the slave side of the fragmenter supports
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// against the master (here the main memory bus). Specifying alwaysMin as
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// true results in all messages being fragmented to the minimal size
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// (32 byte). In TL1 terms, slaves
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// correspond roughly to managers and masters to clients (confusingly…).
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val fragmenter = TLFragmenter(32, 64, alwaysMin=true)
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val response_data = Output(UInt(256.W))
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val response_valid = Output(Bool())
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// no ready, as the mig does not wait
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})
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// TODO: right TL/memory node chain?
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memory.node := fragmenter := memBuses.head.toDRAMController(Some("ml507mig"))()
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override def desiredName: String = "memory_controller"
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}
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class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyModule {
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class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extends LazyModule {
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// Corresponds to MIG interface with 64 bit width and a burst length of 4
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val width = 256
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val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
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@ -56,6 +58,15 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
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// the data width (size signal, see below).
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val port_sys = new MemorySysIO
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val port_ddr2 = new MemoryDDR2IO
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})
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val controller = Module(new MemoryController)
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io.port_sys <> controller.io.sys
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io.port_ddr2 <> controller.io.ddr2
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// in: TLBundle, edge: TLEdgeIn
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val (in, edge) = node.in(0)
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@ -102,3 +113,28 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
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in.e.ready := Bool(true)
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}
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}
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class XilinxML507MIG(c : XilinxML507MIGParams)(implicit p: Parameters) extends LazyModule {
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// The Fragmenter will not fragment messages <= 32 bytes, so all
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// slaves have to support this size. 64 byte specifies the maximum
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// supported transfer size that the slave side of the fragmenter supports
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// against the master (here the main memory bus). Specifying alwaysMin as
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// true results in all messages being fragmented to the minimal size
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// (32 byte). In TL1 terms, slaves correspond roughly to managers and
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// masters to clients (confusingly…).
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val fragmenter = LazyModule(new TLFragmenter(32, 64, alwaysMin=true))
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val island = LazyModule(new XilinxML507MIGToTL(c))
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val node: TLInwardNode =
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island.node := fragmenter.node
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val port_sys = new MemorySysIO
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val port_ddr2 = new MemoryDDR2IO
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})
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io.port_sys <> island.module.io.port_sys
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io.port_ddr2 <> island.module.io.port_ddr2
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}
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}
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@ -0,0 +1,58 @@
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// See LICENSE.SiFive for license details.
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package sifive.fpgashells.devices.xilinx.xilinxml507mig
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import Chisel._
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import chisel3.core.{Input, Output}
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import chisel3.experimental.Analog
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.BaseSubsystem
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case object MemoryML507Key extends Field[XilinxML507MIGParams]
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trait HasMemoryML507 { this: BaseSubsystem =>
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val memory = LazyModule(new XilinxML507MIG(p(MemoryML507Key)))
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memory.node := memBuses.head.toDRAMController(Some("xilinxml507mig"))()
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}
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class MemorySysIO extends Bundle {
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val clk0 = Input(Clock())
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val clk90 = Input(Clock())
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val clkdiv0 = Input(Clock())
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val clk_locked = Input(Bool())
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val clk_idelay = Input(Clock())
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val reset = Input(Bool())
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}
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class MemoryDDR2IO extends Bundle {
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val dq = Analog(64.W)
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val a = Output(Bits(13.W))
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val ba = Output(Bits(2.W))
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val ras_n = Output(Bits(1.W))
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val cas_n = Output(Bits(1.W))
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val we_n = Output(Bits(1.W))
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val cs_n = Output(Bits(1.W))
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val odt = Output(Bits(1.W))
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val cke = Output(Bits(1.W))
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val dm = Output(Bits(8.W))
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val dqs = Analog(8.W)
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val dqs_n = Analog(8.W)
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val ck = Output(Bits(2.W))
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val ck_n = Output(Bits(2.W))
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}
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trait HasMemoryML507Bundle {
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val ddr_sys: MemorySysIO
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val ddr2: MemoryDDR2IO
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}
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trait HasMemoryML507ModuleImp extends LazyModuleImp with HasMemoryML507Bundle {
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val outer: HasMemoryML507
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val ddr_sys = IO(new MemorySysIO)
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val ddr2 = IO(new MemoryDDR2IO)
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ddr_sys <> outer.memory.module.io.port_sys
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ddr2 <> outer.memory.module.io.port_ddr2
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}
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@ -15,6 +15,7 @@ import sifive.blocks.devices.uart._
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import sifive.blocks.devices.chiplink._
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import sifive.blocks.devices.terminal._
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import sifive.fpgashells.devices.xilinx.xilinxml507mig._
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import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_dvi_clock, ml507_sys_clock, vc707reset}
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//-------------------------------------------------------------------------
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@ -79,6 +80,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val reset_led = IO(Output(Bool()))
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val dvi = IO(new TerminalDVIIO)
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val ddr2 = IO(new MemoryDDR2IO)
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//-----------------------------------------------------------------------
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// Wire declrations
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@ -159,6 +161,14 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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dut.terminal.reset := dvi_reset
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}
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//-----------------------------------------------------------------------
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// Memory controller
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//-----------------------------------------------------------------------
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def connectDDRMemory(dut: HasMemoryML507ModuleImp): Unit = {
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ddr2 <> dut.ddr2
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}
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//-----------------------------------------------------------------------
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// UART
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//-----------------------------------------------------------------------
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