Fix memory controller signal name

src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala

@@ -20,7 +20,7 @@ class MemoryController extends BlackBox {
         val ddr2 = new MemoryDDR2IO
 
         val request_addr = Input(UInt(28.W))
-        val request_read = Input(Bool())
+        val request_type = Input(Bool())
         val request_data = Input(UInt(256.W))
         val request_mask = Input(UInt(32.W))
         val request_valid = Input(Bool())