Document address extraction for the mig
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@ -44,6 +44,9 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
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// Corresponds to MIG interface with 64 bit width and a burst length of 4
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val width = 256
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val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
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val address_range = AddressRange.fromSets(c.address).head
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require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported")
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val crossing = AsynchronousCrossing(8)
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val device = new MemoryDevice
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@ -90,13 +93,18 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
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// with respect to the size and address. So we can directly forward
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// the mask, (relative) address and data to the MIG interface.
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// An AddressSet is always aligned, so we don't need to subtract the
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// base address, we can just take the lower bits. The lowest 5 bits
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// are used for indexing the 32 byte word of the MIG.
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val address = in.a.bits.address(27, 0) & "hFFFFFE0".U
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// Save the source, size and type of the requests in a queue so we
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// can synthesize the right responses in fifo order. The length also
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// determines the maximum number of in-flight requests.
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val ack_queue = Module(new Queue(new ResponseQueueIO, 4))
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// Pass data directly to the controller
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controller.io.request_addr := in.a.bits.address(27, 0) & "hFFFFFE0".U
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controller.io.request_addr := address
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controller.io.request_type := !edge.hasData(in.a.bits)
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controller.io.request_data := in.a.bits.data
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// TL uses high to indicate valid data while mig uses low
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