  Henry StylesandWesley W. Terpstra
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045b290fbd
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VC707 JTAG support throught XM105 FMC or reuse of LCD header
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2018-02-08 07:21:44 -08:00 |
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Henry StylesandWesley W. Terpstra
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f9dc552ddc
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Xilinx unisim typo
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2018-02-08 07:21:44 -08:00 |
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Henry StylesandWesley W. Terpstra
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33c88b8cc4
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Move Xilinx unisims into separate file
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2018-02-08 07:21:44 -08:00 |
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 Henry StylesandGitHub
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ba7beb676d
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Merge pull request #14 from sifive/vc707_mig_pcie_traits
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits
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2017-11-01 16:58:44 -07:00 |
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Henry Styles
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e1bfb75188
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
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2017-11-01 14:23:07 -07:00 |
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Henry StylesandGitHub
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eaf1c3ed54
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Merge pull request #11 from sifive/vc707_use_ip_io_bundles
VC707 use IP IO bundles
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2017-10-24 17:49:31 -07:00 |
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Henry Styles
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dc6bb40d1b
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VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP
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2017-10-23 17:27:36 -07:00 |
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Henry Styles
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61b167e8d9
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VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
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2017-10-23 16:53:59 -07:00 |
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Henry StylesandGitHub
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e9019d7570
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Merge pull request #5 from sifive/vivado_vsrcs_using_file
Use a file instead of environment variable to pass VSRCS into Vivado
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2017-09-19 14:13:36 -07:00 |
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Henry Styles
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97e628639a
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Use a file instead of environment variable to pass VSRCS into Vivado
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2017-09-19 14:12:23 -07:00 |
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Henry Styles
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2bed0c30dc
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correct invoke of board specific ip.tcl
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2017-09-08 23:20:55 -07:00 |
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Henry StylesandGitHub
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07b2ae07d2
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Merge pull request #4 from sifive/vc707_2GB
Support both 4G and 1GB DIMM configuration for VC707
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2017-09-08 16:09:18 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Henry StylesandGitHub
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385ffa7d9a
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Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:42:32 -07:00 |
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Henry Styles
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b7ee0ab0f0
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:41:12 -07:00 |
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