Andrew Waterman
fee5d2b1ea
Remove parameters for some things that aren't parameterizable
...
Heads up @colinschmidt and @ccelio. I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them. Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
2016-08-19 12:04:13 -07:00
Andrew Waterman
5164f947c0
Validate mstatus.mpp/dcsr.prv values on MRET/DRET
...
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
2016-08-17 15:39:34 -07:00
Andrew Waterman
2d1d7266f5
Fix RV64 badaddr value on instruction faults with large addresses
...
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
2016-08-15 23:09:09 -07:00
Howard Mao
38e0967816
strip DMA and RoCC CSRs out of rocket and uncore ( #201 )
2016-08-15 23:08:55 -07:00
Andrew Waterman
a857b08c59
[rocket] compute D$ tag bits based upon # of arbiter ports
2016-08-09 14:40:48 -07:00
Andrew Waterman
5d4f6383f2
[rocket] Automatically kill D$ access on address exceptions
...
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
2016-08-02 17:20:49 -07:00
Andrew Waterman
b54db0ba23
[rocket] don't update BTB on not-taken branches
...
Only update the BHT; don't set the target prediction to pc+4.
2016-08-02 17:20:49 -07:00
Andrew Waterman
7e9d139e49
[rocket] remove rocket-specific require() from HasCoreParameters
2016-08-02 15:19:48 -07:00
Andrew Waterman
832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
Andrew Waterman
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
Ben Keller
c069e66056
Modify the RoCC interface to include status in the command queue. ( #41 )
...
This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.
This addresses the first half of #40 .
2016-07-18 17:40:50 -07:00
mwachs5
cff8de9814
Use new Mul/Div parameters vs UseFastMulDiv ( #48 )
...
* Use new Mul/Div parameters vs UseFastMulDiv
* Rename MulDivUnroll to MulUnroll
2016-07-15 15:41:20 -07:00
Andrew Waterman
3d0b92afd7
Misc code cleanup
2016-07-14 12:09:34 -07:00
Andrew Waterman
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
Andrew Waterman
f3e22984d5
Remove uarch counters
...
These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
Howard Mao
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
Andrew Waterman
c10691b616
Don't take interrupts on instructions in branch shadow
...
In situations like
j 1f
nop
1: nop
the interrupt could be taken on the first nop.
2016-06-28 12:47:49 -07:00
Andrew Waterman
a70dee17ea
Make RoCC energy-saving logic mirror same for D$
2016-06-28 12:47:45 -07:00
Andrew Waterman
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
Andrew Waterman
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
Andrew Waterman
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
Andrew Waterman
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
Andrew Waterman
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
Andrew Waterman
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
Andrew Waterman
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
Andrew Waterman
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
Andrew Waterman
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
Andrew Waterman
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
Andrew Waterman
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
Andrew Waterman
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
Andrew Waterman
9aa724706e
Don't include RV64 instructions in RV32 decode table
2016-05-25 14:26:45 -07:00
Andrew Waterman
354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
...
This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
Andrew Waterman
4aef567a80
Fix MMIO bug: replay_next wasn't set
2016-05-13 17:59:53 -07:00
Andrew Waterman
742c05d6a7
Pipeline D$->I$ control paths
...
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
2016-05-13 17:07:28 -07:00
Colin Schmidt
8fa2de0816
chisel3 fix to RoCC connections honor last connect
2016-05-05 18:09:48 -07:00
Andrew Waterman
f784f4da93
Rename PRCICoreIO to PRCITileIO
2016-05-02 18:08:01 -07:00
Andrew Waterman
83fa489cef
Stop using HTIF CSR port
...
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
Andrew Waterman
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
Howard Mao
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
Andrew Waterman
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Andrew Waterman
37b9051762
No need to validate npc if BTB is disabled
2016-04-01 15:54:57 -07:00
Andrew Waterman
7ae44d4905
Add RV32 support
2016-03-10 17:32:00 -08:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
Howard Mao
d51c127646
fix deprecation warnings in rocket.scala
2016-01-13 22:08:06 -08:00
Howard Mao
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
Andrew Waterman
e203b8b378
Make ALU generic for zscale
2015-11-24 19:17:07 -08:00