Andrew Waterman
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a87ad06780
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Automatically infer rocketCAM address width
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2011-12-06 02:05:40 -08:00 |
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Rimas Avizienis
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fa784d1d7d
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made setReadLatency argument a parameter defined in consts.scala
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2011-12-05 00:33:17 -08:00 |
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Rimas Avizienis
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ff95cacb55
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icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
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2011-12-04 01:18:38 -08:00 |
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Rimas Avizienis
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e894b79870
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caches now use Mem4() memories for tag+data arrays
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2011-12-03 19:41:15 -08:00 |
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Rimas Avizienis
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c580180b66
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tweaks to cache/SRAM interface for TSMC65 SRAMs
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2011-12-02 02:01:08 -08:00 |
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Rimas Avizienis
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e70b41241c
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changed branch addr generation to get it off critical path
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2011-12-02 01:56:17 -08:00 |
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Rimas Avizienis
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cf1965493b
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renamed SRAM modules to match TSMC65 MC generated SRAMs
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2011-12-01 13:14:33 -08:00 |
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Rimas Avizienis
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da2fdf4f85
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fixed console i/o
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2011-11-30 22:51:59 -08:00 |
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Rimas Avizienis
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b2894671f6
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2011-11-30 21:55:13 -08:00 |
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Rimas Avizienis
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bc44572d99
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bugfixes due to new hcl jar file
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2011-11-30 21:54:55 -08:00 |
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Andrew Waterman
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8f3927fdfa
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queue data type is now templated
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2011-11-30 18:08:26 -08:00 |
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Rimas Avizienis
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11f0e3daf4
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more cleanup
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2011-11-18 00:17:30 -08:00 |
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Rimas Avizienis
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c42d8149b7
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
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2011-11-17 23:50:45 -08:00 |
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Rimas Avizienis
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5a322ff00c
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fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
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2011-11-17 11:17:37 -08:00 |
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Rimas Avizienis
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80b4253318
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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2011-11-16 02:04:28 -08:00 |
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Rimas Avizienis
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886857fa47
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writes of PC weren't being sign extended
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2011-11-15 18:07:36 -08:00 |
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Rimas Avizienis
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fc0f20643a
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cleanup
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2011-11-15 18:06:41 -08:00 |
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Rimas Avizienis
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ae98956e6b
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more amo fixes, added more options to testharness to control debug messages
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2011-11-15 02:43:51 -08:00 |
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Rimas Avizienis
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82a636ff55
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AMOADD, AMOAND, AMOOR, AMOSWAP working
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2011-11-15 00:51:45 -08:00 |
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Rimas Avizienis
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48cec01710
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updated riscv-bmarks and riscv-tests to build with new toolchain
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2011-11-15 00:11:22 -08:00 |
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Rimas Avizienis
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db87924fbf
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made eret instruction take an illegal inst exception when ET is set
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2011-11-14 14:35:10 -08:00 |
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Rimas Avizienis
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cd6e463320
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added ei and di instructions
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2011-11-14 13:48:49 -08:00 |
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Rimas Avizienis
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b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
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2011-11-14 04:13:13 -08:00 |
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Rimas Avizienis
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890bfa7c48
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added IPIs and timer interrupts
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2011-11-14 03:24:02 -08:00 |
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Rimas Avizienis
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5b29765917
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synced up with supervisor mode state in latest ISA simulator
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2011-11-14 01:37:20 -08:00 |
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Rimas Avizienis
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9d3471a569
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more cache fixes, more test harness debug output
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2011-11-13 23:32:18 -08:00 |
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Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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29d44b8bc5
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fixed typo that broke illegal instruction exception
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2011-11-13 01:17:33 -08:00 |
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Rimas Avizienis
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7b3c34a341
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regenerated instruction encodings using parse-opcodes
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2011-11-13 00:59:02 -08:00 |
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Rimas Avizienis
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44419511b7
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timer interrupt fixes
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2011-11-13 00:32:08 -08:00 |
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Rimas Avizienis
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345f950eff
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added timer interrupt support
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2011-11-13 00:27:57 -08:00 |
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Rimas Avizienis
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5f4b15b809
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added ld/st misaligned exceptions
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2011-11-13 00:03:17 -08:00 |
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Rimas Avizienis
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fbd44ea936
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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Rimas Avizienis
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35af912bd2
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cache optimizations, cleanup, and testharness improvement
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2011-11-12 22:13:29 -08:00 |
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Rimas Avizienis
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91c252ad08
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fixing output enable signals for data/tag SRAMs
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2011-11-12 15:47:47 -08:00 |
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Rimas Avizienis
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83d90c4dab
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
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Rimas Avizienis
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44926866b7
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updated itlb
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2011-11-11 18:48:34 -08:00 |
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Rimas Avizienis
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a1ce908541
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dcache/dtlb overhaul
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2011-11-11 18:18:47 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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603ede8bfe
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access faults now write badvaddr PCR register with faulting address
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2011-11-10 02:46:09 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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fbfa356d2a
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fixed eret instruction
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2011-11-10 00:37:00 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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6664af3bc0
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cleanup before adding dtlb
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2011-11-09 23:27:29 -08:00 |
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Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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7130edac8d
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fix for flushed div/mul instructions
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2011-11-07 01:03:47 -08:00 |
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Rimas Avizienis
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9d63087eb2
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changed caches to use separate sram modules for tag and data arrays
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2011-11-07 00:58:25 -08:00 |
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Rimas Avizienis
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4d64099103
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cleanup
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2011-11-04 20:52:21 -07:00 |
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Rimas Avizienis
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2db9ee12bc
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fixed eret instruction, hello world runs
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2011-11-04 15:57:08 -07:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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3a02028a35
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fixes to exception and dcache miss/blocked handling
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2011-11-02 13:32:32 -07:00 |
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Rimas Avizienis
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7a528d6255
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fixes for div/mul hazard checking + cleanup
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2011-11-01 23:14:34 -07:00 |
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Rimas Avizienis
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d8ffecf565
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dcache fix
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2011-11-01 22:10:06 -07:00 |
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Rimas Avizienis
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7479e085ec
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 22:04:45 -07:00 |
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Rimas Avizienis
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3b3d988fde
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 21:25:52 -07:00 |
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Rimas Avizienis
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2b67eee683
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pipeline changes for replay on dcache miss
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2011-11-01 19:05:27 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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ace4c9d13c
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dcache fixes
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2011-10-31 17:17:36 -07:00 |
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Rimas Avizienis
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65f8b2461c
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dcache tweaks
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2011-10-31 16:47:31 -07:00 |
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Rimas Avizienis
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172e561a78
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added once cycle latency store pipelined d$
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2011-10-31 15:37:37 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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