Rimas Avizienis ff95cacb55 icache/dcache tag+data arrays now implemented using Mem4() ... however there seems to be a bug - readLatency needs to be set to 0 for C model to work, and 1 for Verilog model.		2011-12-04 01:18:38 -08:00
..
src/main/scala	icache/dcache tag+data arrays now implemented using Mem4()	2011-12-04 01:18:38 -08:00