63b814fcd7
only run the important (high coverage) tests in regression suite
2016-08-02 10:54:05 -07:00
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
1063d90993
make sure L1 and L2 agree on coherence policy
2016-07-25 12:20:49 -07:00
6a5b2d7f59
fix assembly tests for configurations without VMU and/or user mode
2016-07-22 17:21:57 -07:00
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
40ab0a7960
fix TL width adapter and make it easier to switch inner data width
2016-06-08 15:38:39 -07:00
2cd897e240
Revert "include the unmatched field in CDEMatchError"
...
This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
2086c0d603
Configs: add a parameter to control the memory subsystem interface
2016-06-06 21:35:43 -07:00
2ddada1732
ahb: add mmio_ahb option
2016-06-06 21:35:39 -07:00
7a24527448
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
2016-06-06 21:35:30 -07:00
f3a557b67b
ahb: AHB parameters should be site specific
...
Conflicts:
src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
ff2937a788
include the unmatched field in CDEMatchError
2016-06-06 11:23:20 -07:00
d24c87f8ba
Update PLIC/PRCI address map ( #124 )
2016-06-06 04:51:55 -07:00
ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
...
Closes #116
2016-05-25 18:01:25 -07:00
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
684d902059
Fix PLIC instantiation when S-mode is disabled
2016-05-13 11:22:46 -07:00
6aa708bcee
Disable MMIO by default to avoid disconnected nets
2016-05-11 13:12:39 -07:00
