521 lines
21 KiB
Scala
521 lines
21 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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import groundtest._
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import scala.math.max
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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object ConfigUtils {
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def max_int(values: Int*): Int = {
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values.reduce((a, b) => max(a, b))
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}
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}
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import ConfigUtils._
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class BaseConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
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entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
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for (i <- 0 until site(NTiles))
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entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("plic", MemSize(1<<22, 1<<22, MemAttr(AddrMapProt.RW)))
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new AddrMap(entries)
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}
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lazy val (globalAddrMap, globalAddrHashMap) = {
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val memSize = 1L << 31
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val memAlign = 1L << 30
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val extIOSize = 1L << 30
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val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true))
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val io = AddrMap(
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AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)),
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AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX))))
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val addrMap = AddrMap(
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AddrMapEntry("io", MemSubmap(io.computeSize, io)),
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AddrMapEntry("mem", mem))
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val addrHashMap = new AddrHashMap(addrMap)
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Dump("MEM_BASE", addrHashMap("mem").start)
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Dump("MEM_SIZE", memSize)
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Dump("IO_BASE", addrHashMap("io:ext").start)
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Dump("IO_SIZE", extIOSize)
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(addrMap, addrHashMap)
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}
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def makeConfigString() = {
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val addrMap = globalAddrHashMap
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val plicAddr = addrMap(s"io:int:plic").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "platform {\n"
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res append " vendor ucb;\n"
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res append " arch rocket;\n"
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res append "};\n"
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${addrMap("io:int:rtc").start.toString(16)};\n"
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res append "};\n"
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").region.size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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res append "core {\n"
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for (i <- 0 until site(NTiles)) {
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val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
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val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
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val prciAddr = addrMap(s"io:int:prci$i").start
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${timecmpAddr.toString(16)};\n"
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res append s" ipi 0x${prciAddr.toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append s" };\n"
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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res append '\u0000'
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res.toString.getBytes
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}
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pname match {
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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csrDataBits = site(XLen),
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
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case VPNBits => site(PgLevels) * site(PgLevelBits)
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VAddrBits => site(VPNBits) + site(PgIdxBits)
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case ASIdBits => 7
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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case HastiKey => HastiParameters(
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dataBits = site(XLen),
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addrBits = site(PAddrBits))
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case CacheIdBits => findBy(CacheName)
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case SplitMetadata => findBy(CacheName)
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case ICacheBufferWays => Knob("L1I_BUFFER_WAYS")
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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val (rvi, rvu) =
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if (site(XLen) == 64) (rv64i, rv64u)
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else (rv32i, rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(bmarks)
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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}
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
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case NDmaTransactors => 3
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case NDmaXacts => site(NDmaTransactors) * site(NTiles)
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case NDmaClients => site(NTiles)
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//Rocket Core Constants
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case FetchWidth => 1
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case RetireWidth => 1
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case UseVM => true
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case UseUser => true
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case UsePerfCounters => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case UseFPU => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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true
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}
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case UseAtomics => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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true
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}
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case NExtInterrupts => 2
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case NExtMMIOChannels => 0
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
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case FDivSqrt => true
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XLen)
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x1000)
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case MtvecInit => BigInt(0x1010)
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case MtvecWritable => true
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case ExtraL1Clients => 1 // HTIF // TODO not really a parameter
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
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nCachingClients = site(NTiles),
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nCachelessClients = site(ExtraL1Clients) +
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site(NTiles) *
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(1 + (if(site(BuildRoCC).isEmpty) 0
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else site(RoccNMemChannels))),
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maxClientXacts = max_int(
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// L1 cache
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site(NMSHRs) + 1,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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val addrMap = globalAddrHashMap
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = addrMap.nEntries - 1,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBits = site(CacheBlockBytes) * 8)
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}
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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case NTiles => Knob("NTILES")
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
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case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
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case BankIdLSB => 0
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseHtifClockDiv => true
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case GlobalAddrHashMap => globalAddrHashMap
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS_PER_MEM_CHANNEL" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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case "L1I_BUFFER_WAYS" => false
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case _ => throw new CDEMatchError
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}
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)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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class With2Cores extends Config(knobValues = { case "NTILES" => 2; case _ => throw new CDEMatchError })
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class With4Cores extends Config(knobValues = { case "NTILES" => 4; case _ => throw new CDEMatchError })
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class With8Cores extends Config(knobValues = { case "NTILES" => 8; case _ => throw new CDEMatchError })
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class With2BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 2; case _ => throw new CDEMatchError })
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class With4BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 4; case _ => throw new CDEMatchError })
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class With8BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 8; case _ => throw new CDEMatchError })
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class With2MemoryChannels extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 2)
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case _ => throw new CDEMatchError
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}
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)
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class With4MemoryChannels extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 4)
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case _ => throw new CDEMatchError
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}
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)
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class With8MemoryChannels extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 8)
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case _ => throw new CDEMatchError
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}
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)
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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(site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
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case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
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case SplitMetadata => Knob("L2_SPLIT_METADATA")
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheId => id
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case CacheName => "L2Bank"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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case L2Replacer => () => new SeqRandom(site(NWays))
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case _ => throw new CDEMatchError
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
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)
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class WithPLRU extends Config(
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(pname, site, here) => pname match {
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case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
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case _ => throw new CDEMatchError
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})
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class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048; case _ => throw new CDEMatchError })
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class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024; case _ => throw new CDEMatchError })
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class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512; case _ => throw new CDEMatchError })
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class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 256; case _ => throw new CDEMatchError })
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class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128; case _ => throw new CDEMatchError })
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class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64; case _ => throw new CDEMatchError })
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class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1; case _ => throw new CDEMatchError })
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class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2; case _ => throw new CDEMatchError })
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class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4; case _ => throw new CDEMatchError })
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseVM => false
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case UseUser => false
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case UseAtomics => false
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case UseFPU => false
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case _ => throw new CDEMatchError
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}
|
|
)
|
|
|
|
class FPGAConfig extends Config (
|
|
(pname,site,here) => pname match {
|
|
case NAcquireTransactors => 4
|
|
case UseHtifClockDiv => false
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class WithBlockingL1 extends Config (
|
|
knobValues = {
|
|
case "L1D_MSHRS" => 0
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
|
|
|
|
class SmallConfig extends Config (
|
|
topDefinitions = { (pname,site,here) => pname match {
|
|
case UseFPU => false
|
|
case FastMulDiv => false
|
|
case NTLBEntries => 4
|
|
case BtbKey => BtbParameters(nEntries = 0)
|
|
case StoreDataQueueDepth => 2
|
|
case ReplayQueueDepth => 2
|
|
case NAcquireTransactors => 2
|
|
case _ => throw new CDEMatchError
|
|
}},
|
|
knobValues = {
|
|
case "L1D_SETS" => 64
|
|
case "L1D_WAYS" => 1
|
|
case "L1I_SETS" => 64
|
|
case "L1I_WAYS" => 1
|
|
case "L1D_MSHRS" => 0
|
|
case _ => throw new CDEMatchError
|
|
}
|
|
)
|
|
|
|
class DefaultFPGASmallConfig extends Config(new SmallConfig ++ new DefaultFPGAConfig)
|
|
|
|
class DefaultRV32Config extends Config(new SmallConfig ++ new WithRV32 ++ new BaseConfig)
|
|
|
|
class ExampleSmallConfig extends Config(new SmallConfig ++ new BaseConfig)
|
|
|
|
class DualBankConfig extends Config(new With2BanksPerMemChannel ++ new BaseConfig)
|
|
class DualBankL2Config extends Config(
|
|
new With2BanksPerMemChannel ++ new WithL2Cache ++ new BaseConfig)
|
|
|
|
class DualChannelConfig extends Config(new With2MemoryChannels ++ new BaseConfig)
|
|
class DualChannelL2Config extends Config(
|
|
new With2MemoryChannels ++ new WithL2Cache ++ new BaseConfig)
|
|
|
|
class DualChannelDualBankConfig extends Config(
|
|
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new BaseConfig)
|
|
class DualChannelDualBankL2Config extends Config(
|
|
new With2MemoryChannels ++ new With2BanksPerMemChannel ++
|
|
new WithL2Cache ++ new BaseConfig)
|
|
|
|
class WithRoccExample extends Config(
|
|
(pname, site, here) => pname match {
|
|
case BuildRoCC => Seq(
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom0,
|
|
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom1,
|
|
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
|
|
nPTWPorts = 1),
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom2,
|
|
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
|
|
|
|
case RoccMaxTaggedMemXacts => 1
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
|
|
|
|
class WithDmaController extends Config(
|
|
(pname, site, here) => pname match {
|
|
case BuildRoCC => Seq(
|
|
RoccParameters(
|
|
opcodes = OpcodeSet.custom2,
|
|
generator = (p: Parameters) => Module(new DmaController()(p)),
|
|
nPTWPorts = 1,
|
|
csrs = Seq.range(
|
|
DmaCtrlRegNumbers.CSR_BASE,
|
|
DmaCtrlRegNumbers.CSR_END)))
|
|
case RoccMaxTaggedMemXacts => 1
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class WithStreamLoopback extends Config(
|
|
(pname, site, here) => pname match {
|
|
case UseStreamLoopback => true
|
|
case StreamLoopbackSize => 128
|
|
case StreamLoopbackWidth => 64
|
|
case _ => throw new CDEMatchError
|
|
})
|
|
|
|
class DmaControllerConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultL2Config)
|
|
class DmaControllerFPGAConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultFPGAConfig)
|
|
|
|
class SmallL2Config extends Config(
|
|
new With2MemoryChannels ++ new With4BanksPerMemChannel ++
|
|
new WithL2Capacity256 ++ new DefaultL2Config)
|
|
|
|
class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity256 ++ new DefaultL2Config)
|
|
class DualChannelBenchmarkConfig extends Config(new With2MemoryChannels ++ new SingleChannelBenchmarkConfig)
|
|
class QuadChannelBenchmarkConfig extends Config(new With4MemoryChannels ++ new SingleChannelBenchmarkConfig)
|
|
class OctoChannelBenchmarkConfig extends Config(new With8MemoryChannels ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class EightChannelConfig extends Config(new With8MemoryChannels ++ new BaseConfig)
|
|
|
|
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
|
|
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
|
|
|
|
class DualCoreConfig extends Config(new With2Cores ++ new BaseConfig)
|