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Author SHA1 Message Date
Wesley W. Terpstra b11839f5a1 tilelink2: differentiate fast/safe address lookup cases 2016-09-17 17:04:18 -07:00
Wesley W. Terpstra b4baae4214 tilelink2: minimize Xbar decode logic 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra 76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra fa0f119f3c tilelink2: consider the implications of negative address mask 2016-09-17 16:14:22 -07:00
Wesley W. Terpstra e437508548 tilelink2: track interrupt connectivity like in TL2 2016-09-17 14:43:48 -07:00
Wesley W. TerpstraandGitHub fd3ac4653c Merge pull request #311 from ucb-bar/rom-executable 
Rom executable
 2016-09-17 01:28:52 -07:00
Wesley W. Terpstra 01c1886b9d Utils: cacheable only if there is a cache manager 2016-09-17 00:56:21 -07:00
Wesley W. Terpstra 6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra e749558190 ROM: optionally (default: true) executable 2016-09-17 00:19:09 -07:00
Wesley W. Terpstra c70045b8b3 Utils: express cacheability from TL2 to TL1 2016-09-17 00:16:40 -07:00
Wesley W. Terpstra e3d2bd3323 Top: print memory region properties, RWX [C] 2016-09-17 00:16:00 -07:00
Wesley W. TerpstraandGitHub 75c73fce37 Merge pull request #309 from ucb-bar/tl2-addrmap 
Tl2 addrmap
 2016-09-16 19:09:22 -07:00
Wesley W. Terpstra 5c858685aa Utils: support managers with multiple addresses 2016-09-16 18:03:49 -07:00
Wesley W. Terpstra a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
Wesley W. Terpstra b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Wesley W. TerpstraandGitHub 503ce14c98 Merge pull request #307 from ucb-bar/address-shrink 
RR: undefined regs return zeros
 2016-09-16 16:55:35 -07:00
Wesley W. Terpstra dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra 3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra 2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra 023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
Wesley W. TerpstraandAndrew Waterman 4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
Wesley W. TerpstraandAndrew Waterman 943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
Wesley W. Terpstra dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra 2c53620275 chisel3: bump for Irrevocable(Decoupled) constructor 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra 9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra 1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Wesley W. TerpstraandGitHub dfd6bfb454 Merge pull request #287 from ucb-bar/crossing-take-2 
Clock crossing redux
 2016-09-13 19:13:21 -07:00
Wesley W. Terpstra d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra 44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra 3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra 8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. TerpstraandGitHub 33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Wesley W. Terpstra 606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra 7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra 273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra 9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra 42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra 94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Wesley W. Terpstra 7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra 85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra 9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra 26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra 98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra 17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra 488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra 5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Wesley W. TerpstraandGitHub 48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. TerpstraandGitHub 808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Wesley W. Terpstra cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
Wesley W. Terpstra 1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Wesley W. Terpstra 66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra 23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra 53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Wesley W. Terpstra 60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra 99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. TerpstraandHenry Cook 9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Wesley W. Terpstra d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Wesley W. Terpstra aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Wesley W. Terpstra 54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra 314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra 56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra 3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00