tilelink2 RegisterRouterTest: stall on both edges

2016-09-14 18:18:59 -07:00 · 2016-09-14 18:18:59 -07:00 · 1c7d7f9d32
parent d35060b881
commit 1c7d7f9d32
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
@ -133,7 +133,7 @@ object RRTestRequest
      val ovalid = progress && busy
      when (progress) {
        busy := Mux(busy, !oready, ivalid)
-        progress := !oready
+        progress := Mux(busy, !oready, !ivalid)
      } .otherwise {
        progress := lfsr(0)
      }