SRAM: optionally (default: true) executable
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@ -4,12 +4,12 @@ package uncore.tilelink2
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import Chisel._
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
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class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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regionType = RegionType.UNCACHED,
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executable = true,
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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