HintHandler: don't violate Irrevocable rules
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f05222a072
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@ -32,22 +32,36 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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val smartManagers = edgeOut.manager.managers.map(_.supportsHint.max == edgeOut.manager.maxTransfer).reduce(_&&_)
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if (supportManagers && !smartManagers) {
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// State of the Hint bypass
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val counter = RegInit(UInt(0, width = log2Up(edgeOut.manager.maxTransfer/edgeOut.manager.beatBytes)))
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val hintHoldsD = RegInit(Bool(false))
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val outerHoldsD = counter =/= UInt(0)
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// Only one of them can hold it
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assert (!hintHoldsD || !outerHoldsD)
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// Count outer D beats
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val beats1 = edgeOut.numBeats1(out.d.bits)
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when (out.d.fire()) { counter := Mux(outerHoldsD, counter - UInt(1), beats1) }
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// Who wants what?
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true)
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val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
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val hintBitsAtA = handleA && in.a.bits.opcode === TLMessages.Hint
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val hintWantsD = in.a.valid && hintBitsAtA
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val outerWantsD = out.d.valid
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// Prioritize existing D traffic over HintAck (and finish multibeat xfers)
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val beats1 = edgeOut.numBeats1(out.d.bits)
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val counter = RegInit(UInt(0, width = log2Up(edgeOut.manager.maxTransfer/edgeOut.manager.beatBytes)))
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val first = counter === UInt(0)
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when (out.d.fire()) { counter := Mux(first, beats1, counter - UInt(1)) }
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val hintWinsD = hintHoldsD || (!outerHoldsD && !outerWantsD)
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hintHoldsD := hintWantsD && hintWinsD && !in.d.ready
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// Hint can only hold D b/c it still wants it from last cycle
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assert (!hintHoldsD || hintWantsD)
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in.d.valid := out.d.valid || (bypassD && in.a.valid && first)
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out.d.ready := in.d.ready
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in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)))
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in.d.valid := Mux(hintWinsD, hintWantsD, outerWantsD)
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in.d.bits := Mux(hintWinsD, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)), out.d.bits)
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out.d.ready := in.d.ready && !hintHoldsD
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in.a.ready := Mux(bypassD, in.d.ready && first && !out.d.valid, out.a.ready)
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out.a.valid := in.a.valid && !bypassD
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in.a.ready := Mux(hintBitsAtA, hintWinsD && in.d.ready, out.a.ready)
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out.a.valid := in.a.valid && !hintBitsAtA
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out.a.bits := in.a.bits
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} else {
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out.a.valid := in.a.valid
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@ -60,21 +74,35 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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}
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if (supportClients && !smartClients) {
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// State of the Hint bypass
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val counter = RegInit(UInt(0, width = log2Up(edgeIn.client.maxTransfer/edgeIn.manager.beatBytes)))
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val hintHoldsC = RegInit(Bool(false))
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val innerHoldsC = counter =/= UInt(0)
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// Only one of them can hold it
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assert (!hintHoldsC || !innerHoldsC)
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// Count inner C beats
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val beats1 = edgeIn.numBeats1(in.c.bits)
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when (in.c.fire()) { counter := Mux(innerHoldsC, counter - UInt(1), beats1) }
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// Who wants what?
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val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source, edgeOut.size(out.b.bits)) else Bool(true)
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val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint
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val hintBitsAtB = handleB && out.b.bits.opcode === TLMessages.Hint
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val hintWantsC = out.b.valid && hintBitsAtB
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val innerWantsC = in.c.valid
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// Prioritize existing C traffic over HintAck (and finish multibeat xfers)
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val beats1 = edgeIn.numBeats1(in.c.bits)
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val counter = RegInit(UInt(0, width = log2Up(edgeIn.client.maxTransfer/edgeIn.manager.beatBytes)))
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val first = counter === UInt(0)
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when (in.c.fire()) { counter := Mux(first, beats1, counter - UInt(1)) }
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val hintWinsC = hintHoldsC || (!innerHoldsC && !innerWantsC)
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hintHoldsC := hintWantsC && hintWinsC && !out.c.ready
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// Hint can only hold C b/c it still wants it from last cycle
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assert (!hintHoldsC || hintWantsC)
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out.c.valid := in.c.valid || (bypassC && in.b.valid && first)
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in.c.ready := out.c.ready
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out.c.bits := Mux(in.c.valid, in.c.bits, edgeOut.HintAck(out.b.bits))
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out.c.valid := Mux(hintWinsC, hintWantsC, innerWantsC)
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out.c.bits := Mux(hintWinsC, edgeOut.HintAck(out.b.bits), in.c.bits)
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in.c.ready := out.c.ready && !hintHoldsC
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out.b.ready := Mux(bypassC, out.c.ready && first && !in.c.valid, in.b.ready)
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in.b.valid := out.b.valid && !bypassC
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out.b.ready := Mux(hintBitsAtB, hintWinsC && out.c.ready, in.b.ready)
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in.b.valid := out.b.valid && !hintBitsAtB
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in.b.bits := out.b.bits
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} else if (bce) {
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in.b.valid := out.b.valid
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