tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
In order to implement a pass-through RAM Monitor model, we will want to support a variable number of inputs and outputs with BOTH different manager and client parameters on each bundle.
This commit is contained in:
Wesley W. Terpstra
parent
176f385b1d
commit
b587a409a3
@ -24,10 +24,7 @@ abstract class LazyModule
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}
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def name = getClass.getName.split('.').last
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def line = info match {
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case SourceLine(filename, line, col) => s" ($filename:$line:$col)"
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case _ => ""
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}
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def line = sourceLine(info)
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def module: LazyModuleImp
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implicit val lazyModule = this
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@ -50,7 +47,8 @@ object LazyModule
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// Make sure the user put LazyModule around modules in the correct order
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// If this require fails, probably some grandchild was missing a LazyModule
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// ... or you applied LazyModule twice
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require (!stack.isEmpty && (stack.head eq bc))
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require (!stack.isEmpty, s"LazyModule() applied to ${bc.name} twice ${sourceLine(sourceInfo)}")
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require (stack.head eq bc, s"LazyModule() applied to ${bc.name} before ${stack.head.name} ${sourceLine(sourceInfo)}")
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stack = stack.tail
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bc.info = sourceInfo
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bc
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@ -60,7 +58,7 @@ object LazyModule
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abstract class LazyModuleImp(outer: LazyModule) extends Module
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{
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// .module had better not be accessed while LazyModules are still being built!
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require (LazyModule.stack.isEmpty)
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require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
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override def desiredName = outer.name
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outer.instantiate()
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@ -29,39 +29,46 @@ class RootNode
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}
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class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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private val oFn: Option[Seq[PO] => PO],
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private val iFn: Option[Seq[PI] => PI],
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private val oFn: (Int, Seq[PO]) => Seq[PO],
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private val iFn: (Int, Seq[PI]) => Seq[PI],
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private val numPO: Range.Inclusive,
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private val numPI: Range.Inclusive) extends RootNode
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{
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// At least 0 ports must be supported
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require (!numPO.isEmpty)
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require (!numPI.isEmpty)
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require (numPO.start >= 0)
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require (numPI.start >= 0)
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def name = lazyModule.name + "." + getClass.getName.split('.').last
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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val noOs = numPO.size == 1 && numPO.contains(0)
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (noOs || oFn.isDefined)
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require (noIs || iFn.isDefined)
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private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accPO = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private val accPI = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private var oRealized = false
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private var iRealized = false
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def name = lazyModule.name + "." + getClass.getName.split('.').last
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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protected def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
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private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
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lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
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lazy val edgesIn = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
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private lazy val oParams : Seq[PO] = {
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val o = oFn(oPorts.size, iPorts.map{ case (i, n) => n.oParams(i) })
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reqE(oPorts.size, o.size)
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o
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}
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private lazy val iParams : Seq[PI] = {
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val i = iFn(iPorts.size, oPorts.map{ case (o, n) => n.iParams(o) })
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reqE(i.size, iPorts.size)
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i
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}
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => imp.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => imp.edgeI(n.oParams(o), i) }
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lazy val bundleOut = imp.bundleO(edgesOut)
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lazy val bundleIn = imp.bundleI(edgesIn)
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@ -71,14 +78,15 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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// source.edge(sink)
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protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
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require (!noOs)
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require (!oRealized)
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require (!x.noIs)
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require (!x.iRealized)
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val info = sourceLine(sourceInfo, " at ", "")
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require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
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require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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require (!x.noIs, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink" + info)
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require (!x.iRealized, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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val i = x.accPI.size
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val o = accPO.size
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accPO += x
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x.accPI += this
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accPO += ((i, x))
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x.accPI += ((o, this))
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() => {
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imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
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}
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@ -86,7 +94,7 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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}
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class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
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extends BaseNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
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class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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@ -101,21 +109,21 @@ class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) exte
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}
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class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
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extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
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extends BaseNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
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{
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require (num.end >= 1)
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require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
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}
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class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
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extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
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extends BaseNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
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{
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require (num.end >= 1)
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require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
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}
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class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
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extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
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extends BaseNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
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{
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require (numPO.end >= 1)
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require (numPI.end >= 1)
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require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
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require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
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}
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@ -1,6 +1,7 @@
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package uncore
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import Chisel._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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package object tilelink2
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{
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@ -9,4 +10,9 @@ package object tilelink2
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def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
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case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
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case _ => ""
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}
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}
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