Merge pull request #307 from ucb-bar/address-shrink
RR: undefined regs return zeros
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commit
503ce14c98
@ -25,13 +25,25 @@ object AddressDecoder
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// Verify the user did not give us an impossible problem
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ports.combinations(2).foreach { case Seq(x, y) =>
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x.foreach { a => y.foreach { b =>
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require (!a.overlaps(b)) // it must be possible to disambiguate addresses!
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require (!a.overlaps(b)) // it must be possible to disambiguate ports!
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} }
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}
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val maxBits = log2Ceil(ports.map(_.map(_.max).max).max + 1)
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val bits = (0 until maxBits).map(BigInt(1) << _).toSeq
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val selected = recurse(Seq(ports.map(_.sorted).sorted(portOrder)), bits)
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selected.reduceLeft(_ | _)
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val output = selected.reduceLeft(_ | _)
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// Modify the AddressSets to allow the new wider match functions
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val widePorts = ports.map { _.map { _.widen(~output) } }
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// Verify that it remains possible to disambiguate all ports
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widePorts.combinations(2).foreach { case Seq(x, y) =>
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x.foreach { a => y.foreach { b =>
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require (!a.overlaps(b))
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} }
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}
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output
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}
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// A simpler version that works for a Seq[Int]
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@ -51,11 +63,12 @@ object AddressDecoder
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// pick the bit which minimizes the number of ports in each partition
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// as a secondary goal, reduce the number of AddressSets within a partition
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val bigValue = 100000
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def bitScore(partitions: Partitions): Int = {
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def bitScore(partitions: Partitions): Seq[Int] = {
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val maxPortsPerPartition = partitions.map(_.size).max
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val sumPortsPerPartition = partitions.map(_.size).sum
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val maxSetsPerPartition = partitions.map(_.map(_.size).sum).max
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maxPortsPerPartition * bigValue + maxSetsPerPartition
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val sumSetsPerPartition = partitions.map(_.map(_.size).sum).sum
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Seq(maxPortsPerPartition, sumPortsPerPartition, maxSetsPerPartition, sumSetsPerPartition)
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}
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def partitionPort(port: Port, bit: BigInt): (Port, Port) = {
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@ -77,8 +90,8 @@ object AddressDecoder
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def partitionPartitions(partitions: Partitions, bit: BigInt): Partitions = {
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val partitioned_partitions = partitions.map(p => partitionPorts(p, bit))
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val case_a_partitions = partitioned_partitions.map(_._1)
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val case_b_partitions = partitioned_partitions.map(_._2)
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val case_a_partitions = partitioned_partitions.map(_._1).filter(!_.isEmpty)
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val case_b_partitions = partitioned_partitions.map(_._2).filter(!_.isEmpty)
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val new_partitions = (case_a_partitions ++ case_b_partitions).sorted(partitionOrder)
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// Prevent combinational memory explosion; if two partitions are equal, keep only one
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// Note: AddressSets in a port are sorted, and ports in a partition are sorted.
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@ -106,9 +119,9 @@ object AddressDecoder
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val score = bitScore(result)
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(score, bit, result)
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}
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val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Int, BigInt, Partitions), Int](_._1))
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val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Iterable[Int]](_._1.toIterable))
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if (debug) println("=> Selected bit 0x%x".format(bestBit))
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if (bestScore < 2*bigValue) {
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if (bestScore(0) <= 1) {
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if (debug) println("---")
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Seq(bestBit)
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} else {
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@ -98,6 +98,9 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
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// A strided slave serves discontiguous ranges
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def strided = alignment1 != mask
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// Widen the match function to ignore all bits in imask
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def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
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// AddressSets have one natural Ordering (the containment order)
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def compare(x: AddressSet) = {
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val primary = (this.base - x.base).signum // smallest address first
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@ -2,8 +2,8 @@
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package uncore.tilelink2
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import Chisel._
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import chisel3.util.{Irrevocable, IrrevocableIO}
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import chisel3._
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import chisel3.util._
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// A bus agnostic register interface to a register-based device
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@ -36,6 +36,23 @@ object RegMapper
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regmap.combinations(2).foreach { case Seq((reg1, _), (reg2, _)) =>
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require (reg1 != reg2)
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}
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// Don't be an asshole...
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regmap.foreach { reg => require (reg._1 >= 0) }
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// Make sure registers fit
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val inParams = in.bits.params
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val inBits = inParams.indexBits
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assert (regmap.map(_._1).max < (1 << inBits))
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val out = Wire(Irrevocable(new RegMapperOutput(inParams)))
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val front = Wire(Irrevocable(new RegMapperInput(inParams)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = regmap.map(_._2.map(_.pipelined)).flatten.reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Convert to and from Bits
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def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
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@ -44,36 +61,33 @@ object RegMapper
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// Find the minimal mask that can decide the register map
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val mask = AddressDecoder(regmap.map(_._1))
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val maskMatch = ~UInt(mask, width = inBits)
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val maskFilter = toBits(mask)
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val maskBits = maskFilter.filter(x => x).size
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// Calculate size and indexes into the register map
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val endIndex = 1 << log2Ceil(regmap.map(_._1).max+1)
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val params = RegMapperParams(log2Up(endIndex), bytes, in.bits.params.extraBits)
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val regSize = 1 << maskBits
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def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
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def regIndexU(x: UInt) = if (maskBits == 0) UInt(0) else
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Cat((maskFilter zip x.toBools).filter(_._1).map(_._2).reverse)
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// Protection flag for undefined registers
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val iRightReg = Array.fill(regSize) { Bool(true) }
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val oRightReg = Array.fill(regSize) { Bool(true) }
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// Flatten the regmap into (RegIndex:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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val index = regIndexI(reg)
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val uint = UInt(reg, width = inBits)
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if (undefZero) {
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iRightReg(index) = ((front.bits.index ^ uint) & maskMatch) === UInt(0)
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oRightReg(index) = ((back .bits.index ^ uint) & maskMatch) === UInt(0)
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}
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// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(reg, index, mask, maskBits))
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(offsets zip fields) map { case (o, f) => (index, o, f) }
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}.flatten
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val out = Wire(Irrevocable(new RegMapperOutput(params)))
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val front = Wire(Irrevocable(new RegMapperInput(params)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = flat.map(_._3.pipelined).reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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@ -122,10 +136,10 @@ object RegMapper
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}
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// Is the selected register ready?
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val rifireMux = Vec(rifire.map(_.reduce(_ && _)))
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val wifireMux = Vec(wifire.map(_.reduce(_ && _)))
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val rofireMux = Vec(rofire.map(_.reduce(_ && _)))
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val wofireMux = Vec(wofire.map(_.reduce(_ && _)))
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val rifireMux = Vec(rifire.zipWithIndex.map { case (seq, i) => !iRightReg(i) || seq.reduce(_ && _)})
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val wifireMux = Vec(wifire.zipWithIndex.map { case (seq, i) => !iRightReg(i) || seq.reduce(_ && _)})
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val rofireMux = Vec(rofire.zipWithIndex.map { case (seq, i) => !oRightReg(i) || seq.reduce(_ && _)})
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val wofireMux = Vec(wofire.zipWithIndex.map { case (seq, i) => !oRightReg(i) || seq.reduce(_ && _)})
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val iindex = regIndexU(front.bits.index)
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val oindex = regIndexU(back .bits.index)
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val iready = Mux(front.bits.read, rifireMux(iindex), wifireMux(iindex))
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@ -138,8 +152,8 @@ object RegMapper
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out.valid := back.valid && oready
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// Which register is touched?
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val frontSel = UIntToOH(iindex)
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val backSel = UIntToOH(oindex)
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val frontSel = UIntToOH(iindex) & Cat(iRightReg.reverse)
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val backSel = UIntToOH(oindex) & Cat(oRightReg.reverse)
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// Include the per-register one-hot selected criteria
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for (reg <- 0 until regSize) {
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@ -159,9 +173,9 @@ object RegMapper
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}
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out.bits.read := back.bits.read
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out.bits.data := Vec(dataOut)(oindex)
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out.bits.data := Mux(Vec(oRightReg)(oindex), Vec(dataOut)(oindex), UInt(0))
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out.bits.extra := back.bits.extra
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(endIndex, out)
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out
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}
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}
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@ -27,7 +27,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
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val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
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val params = RegMapperParams(log2Up(address.mask+1), beatBytes, addrLoEnd)
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val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, addrLoEnd)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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in.bits.read := a.bits.opcode === TLMessages.Get
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in.bits.index := a.bits.addr_hi
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@ -36,10 +36,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
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// Invoke the register map builder
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val (endIndex, out) = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
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// All registers must fit inside the device address space
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require (address.mask >= (endIndex-1)*beatBytes)
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val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
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// No flow control needed
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in.valid := a.valid
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@ -26,15 +26,15 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
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val wdata = UInt(INPUT, width = bits)
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}
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val rfire = io.rvalid && io.rready
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val wfire = io.wvalid && io.wready
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val reg = Reg(UInt(width = bits))
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io.rvalid := rvalid(rfire)
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io.wready := wready(wfire)
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val rvalid_s = rvalid(io.rready)
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val wready_s = wready(io.wvalid)
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io.rvalid := rvalid_s
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io.wready := wready_s
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io.rdata := reg
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when (wfire) { reg := io.wdata }
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when (io.wvalid && wready_s) { reg := io.wdata }
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}
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object RRTestCombinational
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@ -43,19 +43,19 @@ object RRTestCombinational
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def always: Bool => Bool = _ => Bool(true)
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def random: Bool => Bool = { fire =>
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def random: Bool => Bool = { ready =>
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seed = seed + 1
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val lfsr = LFSR16Seed(seed)
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val reg = RegInit(Bool(true))
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reg := Mux(reg, !fire, lfsr(0) && lfsr(1))
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reg
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val valid = RegInit(Bool(true))
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valid := Mux(valid, !ready, lfsr(0) && lfsr(1))
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valid
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}
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def delay(x: Int): Bool => Bool = { fire =>
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def delay(x: Int): Bool => Bool = { ready =>
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val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
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val ready = reg === UInt(0)
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reg := Mux(fire, UInt(x), Mux(ready, UInt(0), reg - UInt(1)))
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ready
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val valid = reg === UInt(0)
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reg := Mux(ready && valid, UInt(x), Mux(valid, UInt(0), reg - UInt(1)))
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valid
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}
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def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
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