tilelink2: add an executable manager parameter
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9442958d67
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ddd93871d8
@ -63,7 +63,7 @@ case class TransferSizes(min: Int, max: Int)
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def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
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def intersect(x: TransferSizes) =
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if (x.max < min || min < x.max) TransferSizes.none
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if (x.max < min || max < x.min) TransferSizes.none
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else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
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}
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@ -101,8 +101,10 @@ case class AddressSet(base: BigInt, mask: BigInt)
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case class TLManagerParameters(
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address: Seq[AddressSet],
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[TLBaseNode] = Seq(),
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// Supports both Acquire+Release+Finish of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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@ -207,7 +209,8 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
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}
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case class TLClientParameters(
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sourceId: IdRange = IdRange(0,1),
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[TLBaseNode] = Seq(),
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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@ -9,6 +9,7 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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