tilelink2: handle bus width=1
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@ -146,7 +146,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val dFragnum = out.d.bits.source(fragmentBits-1, 0)
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val dFirst = acknum === UInt(0)
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val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
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val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Ceil(maxDownSize))
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val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
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val dHasData = edgeOut.hasData(out.d.bits)
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// calculate new acknum
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@ -209,7 +209,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val aOrig = in.a.bits.size
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val aFrag = Mux(aOrig > limit, limit, aOrig)
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val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Ceil(maxDownSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
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val aHasData = node.edgesIn(0).hasData(in.a.bits)
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val aMask = Mux(aHasData, UInt(0), aFragOH1)
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@ -25,7 +25,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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val baseEnd = 0
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val (sizeEnd, sizeOff) = (edge.bundle.sizeBits + baseEnd, baseEnd)
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val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
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val (addrLoEnd, addrLoOff) = (log2Ceil(beatBytes) + sourceEnd, sourceEnd)
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val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
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val params = RegMapperParams(log2Up(address.mask+1), beatBytes, addrLoEnd)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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