tilelink2: differentiate fast/safe address lookup cases
This commit is contained in:
Wesley W. Terpstra
parent
b4baae4214
commit
b11839f5a1
@ -231,7 +231,7 @@ class TLEdgeOut(
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// Transfers
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def Acquire(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Acquire
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a.param := growPermissions
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@ -245,7 +245,7 @@ class TLEdgeOut(
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.Release
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c.param := shrinkPermissions
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@ -260,7 +260,7 @@ class TLEdgeOut(
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.ReleaseData
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c.param := shrinkPermissions
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@ -308,7 +308,7 @@ class TLEdgeOut(
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// Accesses
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def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
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require (manager.anySupportGet)
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val legal = manager.supportsGet(toAddress, lgSize)
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val legal = manager.supportsGetFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Get
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a.param := UInt(0)
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@ -322,7 +322,7 @@ class TLEdgeOut(
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def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt) = {
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require (manager.anySupportPutFull)
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val legal = manager.supportsPutFull(toAddress, lgSize)
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val legal = manager.supportsPutFullFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.PutFullData
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a.param := UInt(0)
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@ -336,7 +336,7 @@ class TLEdgeOut(
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def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask : UInt) = {
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require (manager.anySupportPutPartial)
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val legal = manager.supportsPutPartial(toAddress, lgSize)
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val legal = manager.supportsPutPartialFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.PutPartialData
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a.param := UInt(0)
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@ -350,7 +350,7 @@ class TLEdgeOut(
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def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt) = {
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require (manager.anySupportArithmetic)
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val legal = manager.supportsArithmetic(toAddress, lgSize)
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val legal = manager.supportsArithmeticFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.ArithmeticData
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a.param := atomic
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@ -364,7 +364,7 @@ class TLEdgeOut(
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def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt) = {
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require (manager.anySupportLogical)
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val legal = manager.supportsLogical(toAddress, lgSize)
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val legal = manager.supportsLogicalFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.LogicalData
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a.param := atomic
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@ -378,7 +378,7 @@ class TLEdgeOut(
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def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
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require (manager.anySupportHint)
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val legal = manager.supportsHint(toAddress, lgSize)
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val legal = manager.supportsHintFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Hint
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a.param := param
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@ -445,7 +445,7 @@ class TLEdgeIn(
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// Transfers
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def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
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require (client.anySupportProbe)
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val legal = client.supportsProbe(fromAddress, lgSize)
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val legal = client.supportsProbe(toSource, lgSize)
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val b = Wire(new TLBundleB(bundle))
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b.opcode := TLMessages.Probe
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b.param := capPermissions
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@ -189,7 +189,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// If this is infront of a single manager, these become constants
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val find = manager.find(edgeIn.address(in.a.bits))
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val find = manager.findFast(edgeIn.address(in.a.bits))
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val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
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val maxLgLogical = Mux1H(find, maxLgLogicals)
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val maxLgGet = Mux1H(find, maxLgGets)
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@ -45,7 +45,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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// Who wants what?
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true)
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val handleA = if (passthrough) !edgeOut.manager.supportsHintFast(address, edgeIn.size(in.a.bits)) else Bool(true)
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val hintBitsAtA = handleA && in.a.bits.opcode === TLMessages.Hint
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val hintWantsD = in.a.valid && hintBitsAtA
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val outerWantsD = out.d.valid
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@ -57,7 +57,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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assert (!hintHoldsD || hintWantsD)
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in.d.valid := Mux(hintWinsD, hintWantsD, outerWantsD)
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in.d.bits := Mux(hintWinsD, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)), out.d.bits)
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in.d.bits := Mux(hintWinsD, edgeIn.HintAck(in.a.bits, edgeOut.manager.findIdStartFast(address)), out.d.bits)
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out.d.ready := in.d.ready && !hintHoldsD
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in.a.ready := Mux(hintBitsAtA, hintWinsD && in.d.ready, out.a.ready)
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@ -24,7 +24,7 @@ object TLMonitor
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val mask = edge.full_mask(bundle)
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when (bundle.opcode === TLMessages.Acquire) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Acquire carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'A' channel Acquire smaller than a beat" + extra)
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assert (is_aligned, "'A' channel Acquire address not aligned to size" + extra)
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@ -33,7 +33,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Get) {
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assert (edge.manager.supportsGet(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
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assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Get carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel Get carries invalid param" + extra)
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@ -41,7 +41,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.PutFullData) {
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assert (edge.manager.supportsPutFull(edge.address(bundle), bundle.size), "'A' channel carries PutFull type unsupported by manager" + extra)
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assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type unsupported by manager" + extra)
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assert (source_ok, "'A' channel PutFull carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel PutFull carries invalid param" + extra)
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@ -49,7 +49,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.PutPartialData) {
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assert (edge.manager.supportsPutPartial(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type unsupported by manager" + extra)
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assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type unsupported by manager" + extra)
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assert (source_ok, "'A' channel PutPartial carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel PutPartial carries invalid param" + extra)
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@ -57,7 +57,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.ArithmeticData) {
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assert (edge.manager.supportsArithmetic(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type unsupported by manager" + extra)
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assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Arithmetic carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
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assert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
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@ -65,7 +65,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.LogicalData) {
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assert (edge.manager.supportsLogical(edge.address(bundle), bundle.size), "'A' channel carries Logical type unsupported by manager" + extra)
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assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Logical carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
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assert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
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@ -73,7 +73,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Hint) {
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assert (edge.manager.supportsHint(edge.address(bundle), bundle.size), "'A' channel carries Hint type unsupported by manager" + extra)
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assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Hint carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
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assert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
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@ -84,7 +84,7 @@ object TLMonitor
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assert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
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// Reuse these subexpressions to save some firrtl lines
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val address_ok = edge.manager.contains(bundle.source)
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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val is_aligned = edge.isHiAligned(bundle.addr_hi, bundle.size)
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val mask = edge.full_mask(bundle)
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@ -150,7 +150,7 @@ object TLMonitor
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val source_ok = edge.client.contains(bundle.source)
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val is_aligned = edge.isHiAligned(bundle.addr_hi, bundle.size) && edge.isLoAligned(bundle.addr_lo, bundle.size)
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val address_ok = edge.manager.contains(bundle.source)
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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when (bundle.opcode === TLMessages.ProbeAck) {
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assert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
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@ -171,7 +171,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Release) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (source_ok, "'C' channel Release carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel Release smaller than a beat" + extra)
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assert (is_aligned, "'C' channel Release address not aligned to size" + extra)
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@ -180,7 +180,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.ReleaseData) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel ReleaseData smaller than a beat" + extra)
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assert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
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@ -209,41 +209,59 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
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val anySupportPutPartial = managers.map(!_.supportsPutPartial.none).reduce(_ || _)
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val anySupportHint = managers.map(!_.supportsHint.none) .reduce(_ || _)
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// Which bits suffice to distinguish between all managers
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lazy val routingMask = AddressDecoder(managers.map(_.address))
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// These return Option[TLManagerParameters] for your convenience
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def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
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def findById(id: Int) = managers.find(_.sinkId.contains(id))
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// Synthesizable lookup methods
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def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id)))
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def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start)))
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def findIdStartSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.sinkId.start)))
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def findIdStartFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.sinkId.start)))
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def findIdEndSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.sinkId.end)))
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def findIdEndFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.sinkId.end)))
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// The safe version will check the entire address
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def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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// The fast version assumes the address is valid
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def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Note: returns the actual fifoId + 1 or 0 if None
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def findFifoId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
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def hasFifoId(address: UInt) = Mux1H(find(address), managers.map(m => Bool(m.fifoId.isDefined)))
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def findFifoIdSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
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def findFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
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def hasFifoIdSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => Bool(m.fifoId.isDefined)))
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def hasFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => Bool(m.fifoId.isDefined)))
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lazy val addressMask = AddressDecoder(managers.map(_.address))
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// !!! need a cheaper version of find, where we assume a valid address match exists
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// Does this Port manage this ID/address?
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def contains(address: UInt) = find(address).reduce(_ || _)
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def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
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// containsFast would be useless; it could always be true
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def containsById(id: UInt) = findById(id).reduce(_ || _)
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private def safety_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
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private def safety_helper(member: TLManagerParameters => TransferSizes, select: UInt => Vec[Bool])(address: UInt, lgSize: UInt) = {
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val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
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if (allSame) member(managers(0)).containsLg(lgSize) else {
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Mux1H(find(address), managers.map(member(_).containsLg(lgSize)))
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Mux1H(select(address), managers.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific address
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val supportsAcquire = safety_helper(_.supportsAcquire) _
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val supportsArithmetic = safety_helper(_.supportsArithmetic) _
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val supportsLogical = safety_helper(_.supportsLogical) _
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val supportsGet = safety_helper(_.supportsGet) _
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val supportsPutFull = safety_helper(_.supportsPutFull) _
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val supportsPutPartial = safety_helper(_.supportsPutPartial) _
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val supportsHint = safety_helper(_.supportsHint) _
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val supportsAcquireSafe = safety_helper(_.supportsAcquire, findSafe) _
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val supportsArithmeticSafe = safety_helper(_.supportsArithmetic, findSafe) _
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val supportsLogicalSafe = safety_helper(_.supportsLogical, findSafe) _
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val supportsGetSafe = safety_helper(_.supportsGet, findSafe) _
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val supportsPutFullSafe = safety_helper(_.supportsPutFull, findSafe) _
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val supportsPutPartialSafe = safety_helper(_.supportsPutPartial, findSafe) _
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val supportsHintSafe = safety_helper(_.supportsHint, findSafe) _
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val supportsAcquireFast = safety_helper(_.supportsAcquire, findFast) _
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val supportsArithmeticFast = safety_helper(_.supportsArithmetic, findFast) _
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val supportsLogicalFast = safety_helper(_.supportsLogical, findFast) _
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val supportsGetFast = safety_helper(_.supportsGet, findFast) _
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val supportsPutFullFast = safety_helper(_.supportsPutFull, findFast) _
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val supportsPutPartialFast = safety_helper(_.supportsPutPartial, findFast) _
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val supportsHintFast = safety_helper(_.supportsHint, findFast) _
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}
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case class TLClientParameters(
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@ -119,7 +119,7 @@ class TLRAMModel extends LazyModule
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val a_addr_hi = a.addr_hi | (a_beats1 & ~a_counter1)
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val a_base = edge.address(a)
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val a_mask = edge.mask(a_base, a_size)
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val a_fifo = edge.manager.hasFifoId(a_base)
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val a_fifo = edge.manager.hasFifoIdFast(a_base)
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// Grab the concurrency state we need
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val a_inc_bytes = inc_bytes.map(_.read(a_addr_hi))
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@ -203,7 +203,7 @@ class TLRAMModel extends LazyModule
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val d_base = d_flight.base
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val d_addr_hi = d_base >> shift | (d_beats1 & ~d_counter1)
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val d_mask = edge.mask(d_base, d_size)
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val d_fifo = edge.manager.hasFifoId(d_flight.base)
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val d_fifo = edge.manager.hasFifoIdFast(d_flight.base)
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// Grab the concurrency state we need
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val d_inc_bytes = inc_bytes.map(_.read(d_addr_hi))
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@ -222,7 +222,8 @@ class TLRAMModel extends LazyModule
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|
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// Check the response is correct
|
||||
assert (d_size === d_flight.size)
|
||||
assert (edge.manager.findId(d_flight.base) === d.sink)
|
||||
assert (edge.manager.findIdStartFast(d_flight.base) <= d.sink)
|
||||
assert (edge.manager.findIdEndFast (d_flight.base) > d.sink)
|
||||
// addr_lo is allowed to differ
|
||||
|
||||
when (d_flight.opcode === TLMessages.Hint) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user