tilelink2 AddressDecoder: validate output of optimization
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@ -28,11 +28,22 @@ object AddressDecoder
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require (!a.overlaps(b)) // it must be possible to disambiguate ports!
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} }
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}
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val maxBits = log2Ceil(ports.map(_.map(_.max).max).max + 1)
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val bits = (0 until maxBits).map(BigInt(1) << _).toSeq
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val selected = recurse(Seq(ports.map(_.sorted).sorted(portOrder)), bits)
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selected.reduceLeft(_ | _)
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// port validation via mask expansion
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val output = selected.reduceLeft(_ | _)
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// Modify the AddressSets to allow the new wider match functions
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val widePorts = ports.map { _.map { _.widen(~output) } }
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// Verify that it remains possible to disambiguate all ports
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widePorts.combinations(2).foreach { case Seq(x, y) =>
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x.foreach { a => y.foreach { b =>
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require (!a.overlaps(b))
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} }
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}
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output
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}
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// A simpler version that works for a Seq[Int]
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@ -98,6 +98,9 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
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// A strided slave serves discontiguous ranges
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def strided = alignment1 != mask
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// Widen the match function to ignore all bits in imask
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def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
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// AddressSets have one natural Ordering (the containment order)
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def compare(x: AddressSet) = {
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val primary = (this.base - x.base).signum // smallest address first
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