Andrew Waterman
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6d10115b19
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fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
|
Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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Andrew Waterman
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ed8cc4a1cf
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eliminate D$ probe->WB critical path
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2012-10-04 09:05:14 -07:00 |
|
Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
|
Henry Cook
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b9a9664de5
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uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
|
Andrew Waterman
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0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
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938effc053
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
|
Yunsup Lee
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f633a55722
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fix dcache tag array size
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2012-07-16 22:19:03 -07:00 |
|
Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
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4e5f874266
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update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
|
Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
|
Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
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7f6319047e
|
update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
|
Huy Vo
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7408c9ab69
|
removing wires
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2012-05-24 10:42:39 -07:00 |
|
Henry Cook
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87cbae2c8a
|
Removed defunct ioDmem
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2012-05-07 17:31:39 -07:00 |
|
Henry Cook
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622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
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c13d3e6f88
|
fix probe tag read-modify-write atomicity violation
|
2012-04-26 02:29:31 -07:00 |
|
Henry Cook
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1ed89f1cab
|
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
|
2012-04-24 17:17:42 -07:00 |
|
Henry Cook
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a39080d0b1
|
Fixed abort bug: xact_abort.ready was not pinned high
|
2012-04-24 17:16:40 -07:00 |
|
Andrew Waterman
|
fb4408b150
|
fix AMO replay/coherence deadlock
|
2012-04-15 22:56:02 -07:00 |
|
Andrew Waterman
|
724735f13f
|
fix writeback bug
|
2012-04-13 03:16:48 -07:00 |
|
Andrew Waterman
|
00d934cfac
|
fix coherence bugs in cache
|
2012-04-12 21:57:37 -07:00 |
|
Andrew Waterman
|
c0ec3794bf
|
coherence mostly works now
|
2012-04-10 02:22:45 -07:00 |
|
Henry Cook
|
3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Henry Cook
|
0b4937f70f
|
changed coherence message type names
|
2012-04-09 23:29:31 -07:00 |
|
Henry Cook
|
ed79ec98f7
|
Refactored coherence better from uncore hub, better coherence function names
|
2012-04-09 23:29:31 -07:00 |
|
Yunsup Lee
|
1cddd5de56
|
fix amo locking up problem
|
2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
264732556f
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
|
cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
|
2012-03-16 00:44:16 -07:00 |
|
Andrew Waterman
|
820884c7e6
|
fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
|
2012-03-15 23:08:30 -07:00 |
|
Andrew Waterman
|
4684171ac6
|
fix fence.i for associative caches
|
2012-03-15 21:23:21 -07:00 |
|
Andrew Waterman
|
7dde7099d2
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Andrew Waterman
|
1492457df5
|
add probe replies to HTIF
|
2012-03-13 16:56:47 -07:00 |
|
Andrew Waterman
|
b0f798962c
|
add probe unit
|
2012-03-13 16:43:51 -07:00 |
|
Henry Cook
|
287bc1c262
|
Further refinement of tag_match/tag_hit signals
|
2012-03-13 11:48:12 -07:00 |
|
Andrew Waterman
|
d76b05bde1
|
fix way selection on D$ write upgrades
|
2012-03-13 02:21:02 -07:00 |
|
Henry Cook
|
6229a33dc4
|
fixed cache controller flush unit deadlock
|
2012-03-12 22:01:52 -07:00 |
|
Andrew Waterman
|
8ffdac9526
|
fix D$ store-upgrade bug
loads to the same address as stores that cause an upgrade
could return the old value
|
2012-03-10 15:50:10 -08:00 |
|
Andrew Waterman
|
e3a68848e0
|
fix D$ critical paths and fix verilog build
|
2012-03-09 20:02:51 -08:00 |
|
Henry Cook
|
e591d83e91
|
Fixed global_xact_id propagation bug
|
2012-03-09 11:05:44 -08:00 |
|
Andrew Waterman
|
766bac88f8
|
refactor D$ writebacks and flushes
MSHRs now arbitrate for writebacks and handle flushes.
|
2012-03-09 02:55:46 -08:00 |
|
Andrew Waterman
|
5a7c5772a8
|
clearly distinguish PPN and cache tag
|
2012-03-07 23:11:17 -08:00 |
|
Andrew Waterman
|
c09eeb7fd2
|
fix D$ next-state logic
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
|
2012-03-07 01:42:08 -08:00 |
|