fixed cache controller flush unit deadlock
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@ -722,8 +722,8 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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// reset and flush unit
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val flusher = new FlushUnit(lines)
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val flushed = Reg(resetVal = Bool(true))
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flushed := flushed && (!r_cpu_req_val_ || r_req_flush) || r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && !flushed
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flushed := flushed && (!r_cpu_req_val || r_req_flush) || r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && !flushed
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flusher.io.mshr_req.ready := mshr.io.req.ready
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when (io.cpu.req_val) {
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