Howard Mao
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1ed6d6646d
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move NastiROM and HastiRAM into rom.scala and bram.scala
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2016-05-06 11:31:22 -07:00 |
|
Howard Mao
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77e859760c
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add a Hasti RAM alongside the Nasti ROM
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2016-05-06 11:31:22 -07:00 |
|
Howard Mao
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44740cb6b2
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parameterize Hasti address and data bits
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2016-05-06 11:30:50 -07:00 |
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Howard Mao
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64991d3947
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add AXI to AHB converter
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2016-05-06 11:30:50 -07:00 |
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Howard Mao
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a875eb9c31
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update riscv-tools for bbl fix
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2016-05-05 19:36:34 -07:00 |
|
Colin Schmidt
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8fa2de0816
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chisel3 fix to RoCC connections honor last connect
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2016-05-05 18:09:48 -07:00 |
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Howard Mao
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18ffe7b1ec
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don't use +verbose in vsim .run rule
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2016-05-04 23:01:14 -07:00 |
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Andrew Waterman
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8b06947446
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Run bmarks faster (hopefully)
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2016-05-04 22:47:34 -07:00 |
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Howard Mao
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f1baa4aecc
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update riscv-tests so that mm benchmark doesn't run forever
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2016-05-04 21:28:55 -07:00 |
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Howard Mao
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dfcb73b6c9
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groundtest only needs to write to a single tohost
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2016-05-03 20:21:13 -07:00 |
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Howard Mao
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1882e694e4
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only write to a single tohost location
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2016-05-03 20:20:52 -07:00 |
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Howard Mao
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4045a07eda
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Remove need for separate riscv-tests for groundtest
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2016-05-03 18:29:46 -07:00 |
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Howard Mao
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8f891437b5
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fix CacheFillTest
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2016-05-03 14:57:05 -07:00 |
|
Andrew Waterman
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15f4af19cf
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Remove HTIF CPU port
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2016-05-03 13:55:59 -07:00 |
|
Andrew Waterman
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9dd23a603a
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Remove HTIF port
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2016-05-03 13:41:58 -07:00 |
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Howard Mao
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6cb0979ac4
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fix CacheFillTest
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2016-05-03 13:35:38 -07:00 |
|
Howard Mao
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487d0b356e
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fixes to get groundtest working with priv-1.9 changes
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2016-05-03 13:09:44 -07:00 |
|
Howard Mao
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518d510622
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only write out finish from tile 0 in groundtest
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2016-05-03 13:09:22 -07:00 |
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Howard Mao
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f26c422544
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assert that TileLink router has valid route
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2016-05-03 12:18:06 -07:00 |
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Howard Mao
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b95f095aca
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write to multiple possible tohost locations
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2016-05-02 20:11:20 -07:00 |
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Andrew Waterman
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5352497edb
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MPRV takes effect regardless of privilege mode
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2016-05-02 19:53:25 -07:00 |
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Howard Mao
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4b4e8f7f62
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fixes for priv-1.9 changes
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2016-05-02 18:25:02 -07:00 |
|
Howard Mao
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5cbcc41515
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get rid of unused imports
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2016-05-02 18:23:46 -07:00 |
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Howard Mao
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be21f6962b
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make GlobalAddrHashMap a config variable
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2016-05-02 18:22:43 -07:00 |
|
Andrew Waterman
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c7c8ae5468
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Instantiate PRCI block
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2016-05-02 18:08:33 -07:00 |
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Andrew Waterman
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f784f4da93
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Rename PRCICoreIO to PRCITileIO
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2016-05-02 18:08:01 -07:00 |
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Andrew Waterman
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cc4102f8de
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Add trivial version of PRCI block
It doesn't really do anything besides deliver deliver IPIs yet.
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2016-05-02 17:49:10 -07:00 |
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Andrew Waterman
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6d1e82bddf
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Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
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2016-05-02 15:21:55 -07:00 |
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Andrew Waterman
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72731de25a
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Take a stab at the PRCI-Rocket interface
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2016-05-02 15:20:33 -07:00 |
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Andrew Waterman
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000e20f937
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Remove MIPI; make mip.MSIP read-only
The PRCI block outside the core will provide IPIs eventually
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2016-05-02 15:18:41 -07:00 |
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Andrew Waterman
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83fa489cef
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Stop using HTIF CSR port
The port itself is still present to keep other stuff compiling.
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2016-05-02 14:40:52 -07:00 |
|
Andrew Waterman
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c4d2d29e80
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Stub out debug module, rather than leaving it floating
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2016-04-30 22:37:39 -07:00 |
|
Albert Ou
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0ff4fd0ccd
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Fix IOMSHR to send finishes for stores
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2016-04-30 22:20:29 -07:00 |
|
Andrew Waterman
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46bbbba5e6
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New address map
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2016-04-30 20:59:36 -07:00 |
|
Andrew Waterman
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695c4c5096
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Support both Get and GetBlock on ROMSlave
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2016-04-30 17:34:12 -07:00 |
|
Andrew Waterman
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491184a8f8
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ERET -> xRET; remove mcfgaddr
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2016-04-30 17:32:51 -07:00 |
|
Andrew Waterman
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5af98145b9
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don't signal bad physical address on TLB miss
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2016-04-30 17:31:46 -07:00 |
|
Albert Ou
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6f052a740c
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Add TileLink BRAM slave
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2016-04-29 14:10:44 -07:00 |
|
Andrew Waterman
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d0aa4c722d
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More WIP on new memory map
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2016-04-28 16:15:31 -07:00 |
|
Andrew Waterman
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cae4265f3b
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Change mcfgaddr pointer
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2016-04-28 16:14:05 -07:00 |
|
Andrew Waterman
|
e4ace55d77
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Address Map refactoring
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2016-04-28 16:12:35 -07:00 |
|
Andrew Waterman
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1df68a25fd
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Address Map refactoring
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2016-04-28 16:08:58 -07:00 |
|
Wei Song
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ed5bdf3c23
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print the base address of each SCR as indicated
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2016-04-28 16:31:56 +01:00 |
|
Andrew Waterman
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1f211b37df
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WIP on new memory map
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2016-04-27 14:57:54 -07:00 |
|
Andrew Waterman
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739cf07637
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Remove mtime/mtimecmp
The RTC is now a device that lives on the MMIO bus.
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2016-04-27 14:54:51 -07:00 |
|
Andrew Waterman
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81ff127dc3
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Clean up TileLinkRecursiveInterconnect a bit
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2016-04-27 14:53:11 -07:00 |
|
Andrew Waterman
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c8b1f0801b
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Remove start address option from AddrMapEntries
It appears to never be used, and clutters things. The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
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2016-04-27 14:52:05 -07:00 |
|
Andrew Waterman
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d3dee2c6c6
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support countSlaves on empty address maps
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2016-04-27 14:51:52 -07:00 |
|
Andrew Waterman
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87cecc336f
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Add new RTC as TileLink slave, not AXI master
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2016-04-27 11:55:35 -07:00 |
|
Andrew Waterman
|
fb5c38c186
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Handle invalidate_lr in cache arbiter, not tile
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2016-04-27 11:22:04 -07:00 |
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