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Commit Graph

79 Commits

Author SHA1 Message Date
904f0f3d93 enhance error message when debug enabled
This commit enhances the error message when the user enables waveform dump at runtime but forgets to enable the compile time define.
2018-01-13 13:35:52 -08:00
42e5e92d43 Update TestDriver module to support FSDB
Add support for FSDB waveform dumping using existing API.  Feature is enabled using +define+FSDB.

Change has not been fully regressed (i.e., please don't pull blindly).  Impact on existing knobs is minimal, should not affect existing functionality.  Automated Travis builds should be sufficient to assess.

Alternatively could using +define+VCS.  Chose to introduce new define because multiple simulators support FSDB dumping.
2018-01-09 09:54:34 -08:00
a86a9c5564 Fix omitted parameter (#1014) 2017-09-25 14:11:28 -07:00
cda89fbacb async_reset_reg: Don't randomize the register if rst is asserted anyway 2017-09-20 14:47:00 -07:00
f68390e458 jtag_vpi: Use a parameter for INIT_DELAY vs constant 2017-09-07 09:06:07 -07:00
19eabb6728 jtag_vpi: add some hysterisis for waiting for init_done 2017-09-06 18:13:04 -07:00
81890e3a42 async_reg: Clean up some funky indentation 2017-08-21 16:06:36 -07:00
4f45379863 async_reset_reg: Squash X's the same as for reset reg 2017-08-21 14:33:19 -07:00
fa867bc478 plusarg_reader: make synthesis path a no brainer (#947) 2017-08-10 16:35:30 -07:00
ff1f0170dc changing SystemVerilog params to Verilog style (#801)
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
2017-06-16 22:47:12 -07:00
6a7e6ab325 plusarg_reader: support verilator 2017-06-01 10:59:45 -07:00
6aa13b4e01 JTAG VPI: Make it work without debug_pp flag 2017-05-30 15:46:45 -07:00
618468a06b Make plusarg_reader default args work with VCS (#765)
Resolves #764
2017-05-24 21:38:56 -07:00
7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752)
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
2119df5a60 vsrc: add ClockDivider3 used to simulate unaligned clocks 2017-05-14 15:05:55 -07:00
2faf8ea239 Add +dump-start=N option to VCS
Starts dumping waveform on cycle N.

Can control stop cycle with +max-cycles.
2017-04-20 17:00:46 -07:00
ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
cbc8d2400a debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version 2017-03-27 21:24:44 -07:00
42ca597478 debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
9153a9a733 ClockDivider: add docs to appease the reviewer
... even though this means a delay of 1:30 hours :(
2017-02-17 19:35:08 +01:00
91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs)
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
2017-02-17 14:26:23 +01:00
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
f382ee70da Sanity check compile-time vs simulation-time options
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.

It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
2016-10-24 14:45:34 -07:00
737cf82478 Print out seed if we can (#412)
Now that we have ifdef VCS in here lets use it for something more than compatibility
2016-10-24 12:36:29 -07:00
a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format
This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
2016-10-19 13:26:31 -07:00
9f0fda01b3 Fix Cadence Incisive compile warning
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
dc4c375c7f Silence Verilog compile warning from Cadence Incisive 2016-10-17 15:44:24 -07:00
7f429e8799 Simplify AsyncResetReg
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
2016-10-08 21:29:40 -07:00
23c8b06d4a use $urandom as seed for $random 2016-10-03 17:56:30 -07:00
5ff3d3d61c correctly initialize with seed 2016-10-02 17:31:32 -07:00
1e43512142 jtag: Actually apply the sticky bits 2016-09-29 13:49:34 -07:00
a4b81aebe0 jtag: Apply sticky bits for error and busy according to the current Debug Spec 2016-09-29 13:49:26 -07:00
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
77a0f76289 Cleanup jtag dtm (#342)
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
9acb352cf6 Correct Merge Conflitct -- clock, not clk (#327)
I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
2016-09-21 20:02:01 -07:00
3a809b209f Allow Makefile override of RESET_DELAY (#322) 2016-09-21 18:28:30 -07:00
8e63f4a1a5 Remove ClockToSignal and vice-versa
Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305)
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
a10d058e1a fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
4a7972be31 connect testharness components via member functions (#236)
to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
96a868d388 enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish 2016-08-19 17:14:54 -07:00