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rocket-chip/vsrc
Scott Johnson 9f0fda01b3 Fix Cadence Incisive compile warning
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
..
AsyncResetReg.v util: Do BlackBox Async Set/Reset Registers more properly (#305) 2016-09-16 13:50:09 -07:00
DebugTransportModuleJtag.v jtag: Actually apply the sticky bits 2016-09-29 13:49:34 -07:00
jtag_vpi.tab Add JTAG DTM and test support in simulation 2016-08-19 16:08:17 -07:00
jtag_vpi.v fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
SimDTM.v Write test harness in Chisel 2016-08-15 23:27:27 -07:00
TestDriver.v Fix Cadence Incisive compile warning 2016-10-19 13:23:36 -07:00