ClockDivider2: fix launch alignment of clocks (vcs)

Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.

vsrc/ClockDivider2.v

@@ -0,0 +1,21 @@
+// See LICENSE.SiFive for license details.
+
+/** This black-boxes a Clock Divider.
+  *
+  * Because Chisel does not support
+  * blocking assignments, it is impossible
+  * to create a deterministic divided clock.
+  *
+  *  @param clk_out Divided Clock
+  *  @param clk_in  Clock Input
+  *
+  */
+
+module ClockDivider2 (output reg clk_out, input clk_in);
+
+   initial clk_out = 1'b0;
+   always @(posedge clk_in) begin
+      clk_out = ~clk_out; // Must use =, NOT <=
+   end
+
+endmodule // ClockDivider2