fix warnings in verilog source (#274)
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@ -125,8 +125,8 @@ module DebugTransportModuleJtag (
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assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1};
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wire [3:0] debugAddrBits = DEBUG_ADDR_BITS;
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wire [3:0] debugVersion = DEBUG_VERSION;
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wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
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wire [3:0] debugVersion = DEBUG_VERSION[3:0];
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assign dtminfo = {24'b0, debugAddrBits, debugVersion};
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@ -76,10 +76,6 @@ reg [31:0] data_in;
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integer debug;
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assign tms_o = tms;
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assign tck_o = tck;
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assign tdi_o = tdi;
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initial
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begin
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tck <= #TP 1'b0;
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