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fix warnings in verilog source (#274)

This commit is contained in:
Colin Schmidt 2016-09-12 18:25:35 -07:00 committed by Andrew Waterman
parent 88440ebf89
commit a10d058e1a
2 changed files with 2 additions and 6 deletions
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4
vsrc/DebugTransportModuleJtag.v
View File

@ -125,8 +125,8 @@ module DebugTransportModuleJtag (
assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1};
wire [3:0] debugAddrBits = DEBUG_ADDR_BITS;
wire [3:0] debugVersion = DEBUG_VERSION;
wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
wire [3:0] debugVersion = DEBUG_VERSION[3:0];
assign dtminfo = {24'b0, debugAddrBits, debugVersion};

4
vsrc/jtag_vpi.v
View File

@ -76,10 +76,6 @@ reg [31:0] data_in;
integer debug;
assign tms_o = tms;
assign tck_o = tck;
assign tdi_o = tdi;
initial
begin
tck <= #TP 1'b0;