riscv/rocket-chip
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rocket-chip/vsrc
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Megan Wachs 42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
..
AsyncResetReg.v
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
ClockDivider2.v
ClockDivider: add docs to appease the reviewer
2017-02-17 19:35:08 +01:00
DebugTransportModuleJtag.v
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
jtag_vpi.tab
Add JTAG DTM and test support in simulation
2016-08-19 16:08:17 -07:00
jtag_vpi.v
debug: Breaking change until FESVR is updated as well.
2017-03-27 21:19:08 -07:00
SimDTM.v
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
TestDriver.v
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00