async_reset_reg: Don't randomize the register if rst is asserted anyway

vsrc/AsyncResetReg.v

@@ -54,7 +54,9 @@ module AsyncResetReg (
 `endif
 `ifdef RANDOMIZE_REG_INIT
       _RAND = {1{$random}};
-      q = _RAND[0];
+      if (~rst) begin
+         q = _RAND[0];
+      end
 `endif
    end
 `endif //  `ifdef RANDOMIZE