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changing SystemVerilog params to Verilog style (#801)

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vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
This commit is contained in:
Shreesha Srinath 2017-06-16 22:47:12 -07:00 committed by Wesley W. Terpstra
parent 31415060fe
commit ff1f0170dc
1 changed files with 1 additions and 1 deletions
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vsrc/plusarg_reader.v
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@ -2,7 +2,7 @@
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(string FORMAT="borked=%d", int DEFAULT=0) (
module plusarg_reader #(FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);