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Remove ClockToSignal and vice-versa

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Clock.asUInt and Bool.asClock now suffice.
This commit is contained in:
Andrew Waterman
2016-09-21 16:17:14 -07:00
parent 2ab61f1a71
commit 8e63f4a1a5
4 changed files with 0 additions and 79 deletions
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19
vsrc/ClockToSignal.v
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@ -1,19 +0,0 @@
/* This blackbox is needed by
* Chisel in order to do type conversion.
* It may be useful for some synthesis flows
* as well which require special
* flagging on conversion from data to clock.
*/
module ClockToSignal(
output signal_out,
input clock_in
);
assign signal_out = clock_in;
endmodule // ClockToSignal

18
vsrc/SignalToClock.v
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@ -1,18 +0,0 @@
/* This blackbox is needed by
* Chisel in order to do type conversion.
* It may be useful for some synthesis flows
* as well which require special
* flagging on conversion from data to clock.
*/
module SignalToClock (
output clock_out,
input signal_in
);
assign clock_out = signal_in;
endmodule // SignalToClock